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6770959 |
Semiconductor package without substrate and method of manufacturing same
A semiconductor package without substrate and method of manufacturing the same includes providing an interim substrate which has a front surface covered with a solder mask at selected locations....
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6770979 |
Semiconductor package and substrate thereof
Disclosed is a semiconductor package characterized by having at least one cavity defined in a substrate and at least one buffer pad disposed in the at least one cavity. The semiconductor package...
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6770906 |
Semiconductor reliability test chip
A semiconductor test chip including a plurality of test functions. The test functions of the semiconductor test chip include bond pad pitch and size effects on chip design, wire bond placement...
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6768207 |
Multichip wafer-level package and method for manufacturing the same
A multichip wafer-level package includes a first chip, a second chip, a bump ring and a plurality of bumps. The first chip has a semiconductor device, a first bonding ring surrounding the...
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6768142 |
Circuit component placement
A method for designing an input output cell of an integrated circuit. The input output cell has a required area, a width, and a height. The bonding pad pitch length between adjacent bonding pads of...
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6768212 |
Semiconductor packages and methods for manufacturing such semiconductor packages
A semiconductor package according to the present invention includes a die attachment area for receiving a die attachment material and a stitch bond area for receiving a wire lead from a die. The...
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6768186 |
Semiconductor device and laminated leadframe package
An semiconductor device ( 100 ) comprising a first semiconductor die ( 120 ) and a leadframe ( 200 ). The leadframe includes a first laminate ( 210 ) having a bottom surface formed with a lead (...
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6765296 |
Via-sea layout integrated circuits
An integrated circuit interconnect is provided having a dielectric layer disposed between a wide top metal line and a wide bottom metal line. A via-sea in the dielectric layer connects the wide top...
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6765228 |
Bonding pad with separate bonding and probing areas
A new and improved bonding pad having separate areas for probe needle contact and wire bonding in semiconductor packaging technology. The bonding pad typically has a generally elongated,...
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6765301 |
Integrated circuit bonding device and manufacturing method thereof
An integrated circuit device. The substrate includes a signal connection point and two shielding connection points set at the two sides of the signal connection point. The chip is set on the...
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6764879 |
Semiconductor wafer, semiconductor device, and method for manufacturing the same
A semiconductor wafer of the present invention includes: a plurality of semiconductor chip areas each of which is to be a semiconductor chip; and a cut-off area for separating the plurality of...
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6762431 |
Wafer-level package with test terminals
A wafer-level package includes a semiconductor wafer having at least one semiconductor chip circuit forming region each including a semiconductor chip circuit each provided with test chip terminals...
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6759753 |
Multi-chip package
A multi-chip package includes a transparent substrate, at least two chips, a plurality of connecting terminals, and a molding compound. In this case, the transparent substrate has a conductive...
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6759597 |
Wire bonding to dual metal covered pad surfaces
Wire bonds are made to palladium coated bonded pads on organic dielectric substrates at temperatures below 200° C. A layer of palladium thicker than 14 micro-inches is covered with a thin flash of...
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6756138 |
Micro-electromechanical devices
A device having electrical and mechanical components. The device comprises multiple layers in which: a first layer or set of layers arranged is to function as one or more electrodes or conductors;...
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6756683 |
High-frequency semiconductor device including a semiconductor chip
A semiconductor device includes a silicon substrate with a resistivity being raised by diffusing Au etc. therein, and includes both active elements and passive elements. The active elements are all...
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6753615 |
Optical element module
In a conventional optical element module, a filter substrate mounting an air-core coil thereto is mounted in the vicinity of a light emitting element, and the light emitting element and the...
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6753598 |
Transverse hybrid LOC package
A hybrid semiconductor package is formed from a die having two opposed elongate die edges with conductive bond pads arranged transversely relative to the rows of outer leads. A first portion of...
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6753594 |
Electronic component with a semiconductor chip and fabrication method
The invention relates to an electronic component with a semiconductor chip and a rewiring plate including a bond channel for bond connections between contact surfaces of the semiconductor chip and...
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6747361 |
Semiconductor device and packaging method thereof
A semiconductor chip semiconductor device of the present invention is capable of obtaining a high-quality bare chip (HQC) easily and can retain quality without being affected by the surrounding...
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6747346 |
Container for semiconductor sensor, manufacturing method therefor, and semiconductor sensor device
A container for a semiconductor sensor includes a housing body and a cover. On the upper surface of the housing body outer than the pressure detection room, a groove is provided to trap the gel...
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6743979 |
Bonding pad isolation
An integrated circuit, including a substrate with circuitry formed therein, where the substrate has a peripheral edge. Also included are a top most electrically conductive layer and an underlying...
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6744125 |
Super thin/super thermal ball grid array package
A new method and package is provided for the packaging of semiconductor devices. The method and package starts with a semiconductor substrate, the substrate is pre-baked. In the first embodiment of...
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6740981 |
Semiconductor device including memory unit and semiconductor module including memory units
A semiconductor device comprises a memory unit, a selecting signal terminal, and an identifying unit. The selecting signal terminal receives a memory unit selecting signal which is commonly...
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6740985 |
Structure for bonding pad and method for its fabrication
A copper bonding pad is directly supported by a copper via pad structure, the copper via pad structure having substantially the same geometry and dimensions as the copper bonding pad. The...
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6740978 |
Chip package capable of reducing moisture penetration
A semiconductor chip package is formed to be capable of reducing moisture erosion by configuring the bonding finger, the plating-conduction-line, and the trace on the chip carrier therein in such a...
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6737752 |
Flip-chip package containing a chip and a substrate having differing pitches for electrical connections
A flip-chip package uses a substrate having bond pad spacing that matches terminal spacing on a chip at an elevated temperature that is an expected operating temperature of the chip. The elevated...
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6734093 |
Method for placing active circuits beneath active bonding pads
The present invention provides a bonding pad structure for integrated circuit devices which allows the active circuits to be placed under bonding pads of the device without affecting the...
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6731511 |
Wiring board, method of manufacturing the same, electronic component, and electronic instrument
A wiring board includes a wiring pattern having a lands and a line connected to the land, a substrate supporting the wiring pattern, and a protective film provided over the substrate and having an...
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6730855 |
Electronic element
An wiring board is provided so as to wrap a semiconductor chip, and on the outer surface of wiring board, a plurality of external terminals are provided three-dimensionally, i.e., on the upper,...
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6731014 |
Semiconductor package substrate, semiconductor package
A semiconductor package substrate of the present invention includes a first wiring substrate which has an opening section for mounting a semiconductor chip, and a second wiring substrate which has...
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6730985 |
Semiconductor integrated circuit device
Unnecessary crossing of interconnections are eliminated to reduce the impedance of wiring of an LSI of a semiconductor integrated circuit device. In the semiconductor integrated circuit device of...
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6730996 |
Semiconductor device
In a semiconductor device, at the time of resin sealing, a conductor within the resin is exposed at a surface on which a cooling device is to be mounted. With this configuration, a semiconductor...
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6731013 |
Wiring substrate, semiconductor device and package stack semiconductor device
A wiring substrate of the present invention includes a terminal section, provided on a first surface of an insulating substrate, for wire or flip-chip bondings; a land section, provided on the...
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6727574 |
Semiconductor device and method for manufacturing the same, circuit substrate and electronic apparatus
The invention enhances reliability and achieves higher speeds for semiconductor devices with a stacked structure. A semiconductor device includes a die pad, a plurality of semiconductor chips...
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6727596 |
Semiconductor integrated circuit
Bump areas for signals are spread on upper and lower positions with respect to Vdd and Vss lines in an I/O buffer. Thus, the direction of routing the lines from bumps for signals to the I/O buffers...
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6727590 |
Semiconductor device with internal bonding pad
A semiconductor device has a multilayer interconnection structure in which a plurality of interconnection layers is formed in an insulating film. The multilayer interconnection structure has a...
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6724074 |
Stack semiconductor chip package and lead frame
A stack package has a lead frame and first and second stacked chips. The lead frame comprises first and second lead groups respectively corresponding to the first and second chips and a plurality...
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6720646 |
Power converter with improved lead frame arrangement including stand-up portion
In a semiconductor device, a lead frame is adhered to a base substrate for heat dissipation via an insulating layer, and an outward guided terminal portion is formed by perpendicularly upwardly...
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6720658 |
Semiconductor device having a plurality of conductive layers
In the present invention, the bonding pad is formed in a lattice-like shape. Directly underneath the passivation layer, the etching stopper layer is provided. An opening is made through the...
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6717272 |
Reinforced bond-pad substructure and method for fabricating the same
A semiconductor device for reinforcing a substructure of a bond pad and a method for fabricating the same are provided. According to an embodiment, a semiconductor device for reinforcing a...
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6717270 |
Integrated circuit die I/O cells
An integrated circuit die includes an input/output (I/O) cell. The I/O cell includes active I/O circuitry in a substrate, a plurality of metal interconnect layers, an insulating layer, a first pad,...
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6717253 |
Assembly package with stacked dies and signal transmission plate
An assembly package includes a substrate, a first die, at least one signal transmission plate, at least one second die, a plurality of conductive wires, and a molding compound. The first die is...
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6713881 |
Semiconductor device and method of manufacturing same
Object: To provide sufficient connection strength between the bonding pads and conductor wires in a wire bonding method. Means for Solution: The bonding pads 20 upon a semiconductor chip 18 ...
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6713849 |
Semiconductor utilizing grooves in lead and tab portions of lead frame to prevent peel off between the lead frame and the resin
In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and...
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6713836 |
Packaging structure integrating passive devices
In a leadframe packaging structure, a leadframe includes a plurality of first leads, a plurality of second leads, and a die pad. The first leads define a chip-bonding region in which is arranged...
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6713869 |
Wiring pattern of semiconductor device
A semiconductor package of this invention comprises an electrode pad arranged on a semiconductor chip, a bonding wire, an end of which is coupled to the electrode pad, and a connection pad arranged...
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6713852 |
Semiconductor leadframes plated with thick nickel, minimum palladium, and pure tin
A leadframe for use with integrated circuit chips comprising a base metal having a plated layer of nickel fully covering said base metal; a plated layer of pure tin on said nickel layer,...
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6713880 |
Semiconductor device and method for producing the same, and method for mounting semiconductor device
A semiconductor device includes a semiconductor chip, an insulating layer formed on a region excluding the plurality of electrode pads on the principal surface of the semiconductor chip, a...
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6713870 |
Wafer level chip-scale package
A wafer level chip-scale package comprises a chip including a plurality of metal pads individually formed on each of the bonding pads. In the same metal circuit layer where metal pads exist, bump...
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