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9196581 Flow underfill for microelectronic packages  
A microelectronic assembly includes a first component with first conductive elements; a second component with second conductive elements; a bond metal; and an underfill layer. The posts have a...
9041222 Semiconductor device  
A semiconductor device is provided, which comprises a first semiconductor package, a second semiconductor package, and a connection structure. The first semiconductor package includes a first...
9041221 Electronic component implementing structure intermediate body, electronic component implementing structure body and manufacturing method of electronic component implementing structure body  
An implementing structure intermediate body including: a first chip having a first connection terminal; a second chip having a second connection terminal in a face that faces the first chip; and a...
9040352 Film-assist molded gel-fill cavity package with overflow reservoir  
A semiconductor device package having a cavity formed using film-assisted molding techniques is provided. Through the use of such techniques the cavity can be formed in specific locations in the...
9041177 Semiconductor device with sealing resin  
Various embodiments of the present invention include a semiconductor device, the semiconductor device including a first semiconductor chip disposed on a substrate, a first sealing resin sealing...
9041220 Semiconductor device having stacked memory elements and method of stacking memory elements on a semiconductor device  
A semiconductor device includes a die coupled to a substrate, a first memory device coupled to a surface of the die opposite the substrate and a coupling device coupled between the surface of the...
9040388 Chip assembly with a coreless substrate employing a patterned adhesive layer  
A patterned adhesive layer including holes is employed to attach a coreless substrate layer to a stiffener. The patterned adhesive layer is confined to kerf regions, which are subsequently removed...
9041219 Multi chip package, manufacturing method thereof, and memory system having the multi chip package  
A multi-chip package is provided. The multi-chip package includes a plurality of chips including at least one bad chip and at least one good chip that are stacked and a plurality of through...
9040387 ***WITHDRAWN PATENT AS PER THE LATEST USPTO WITHDRAWN LIST***
Stacked microelectronic packages having patterned sidewall conductors and methods for the fabrication thereof
 
Embodiments of a method for fabricating stacked microelectronic packages are provided, as are embodiments of a stacked microelectronic package. In one embodiment, the method includes arranging...
9035443 Massively parallel interconnect fabric for complex semiconductor devices  
An embodiment of this invention uses a massive parallel interconnect fabric (MPIF) at the flipped interface of a core die substrate (having the core logic blocks) and a context die (used for in...
9035465 Forming semiconductor chip connections  
Various embodiments include semiconductor structures. In one embodiment, the semiconductor structure includes a chip having a body having a polyhedron shape with a pair of opposing sides; and a...
9034692 Integrated circuit packaging system with a flip chip and method of manufacture thereof  
A method of manufacture of an integrated circuit packaging system includes: providing a lead; placing an integrated circuit device, having an external connector, adjacent to and electrically...
9035442 Semiconductor module  
A semiconductor module having a second semiconductor package 200 mounted on a first semiconductor package 100, wherein the first semiconductor package 100 includes: pads 15 formed on the top...
9029241 Photoelectric conversion device, image pickup system and method of manufacturing photoelectric conversion device  
A photoelectric conversion device includes a first semiconductor substrate including a photoelectric conversion unit for generating a signal charge in accordance with an incident light, and a...
9029234 Physical design symmetry and integrated circuits enabling three dimentional (3D) yield optimization for wafer to wafer stacking  
One of the wafers in a semiconductor wafer to wafer stack can be rotated a predefined number of positions, relative to a previous wafer in the stack, and bonded in the position in which the...
9029199 Method for manufacturing semiconductor device  
A method for manufacturing a semiconductor device includes: preparing a semiconductor wafer including a plurality of semiconductor chips arranged in the shape of a matrix, the semiconductor wafer...
9030004 Stacked semiconductor apparatus, system and method of fabrication  
A stacked semiconductor apparatus and method of fabricating same are disclosed. The apparatus includes upper and lower semiconductor devices having a similar pattern of connection elements. When...
9030027 Assembled circuit and electronic component  
An assembled circuit is disclosed, wherein the assembled circuit comprises an inductor having a top surface, a bottom surface and side surfaces, wherein each of a plurality of conductors extends...
9030017 Z-connection using electroless plating  
An assembly includes a substrate having a substrate conductor and a contact at a first surface and a terminal at a second surface for electrically interconnecting the assembly with a component...
9029998 Semiconductor package device  
A semiconductor package device includes a lower package including a lower semiconductor chip mounted on the lower package substrate, a lower molding compound layer disposed on the lower package...
9024451 Integrated lighting apparatus and method of manufacturing the same  
An integrated lighting apparatus comprises a first control device including a semiconductor substrate, an integrated circuit block formed above a first portion of the semiconductor substrate, and...
9024423 Semiconductor device for a DC-DC converter  
A semiconductor chip in which a power MOSFET is placed above a semiconductor chip in which another power MOSFET is formed and they are sealed with an encapsulation resin. The semiconductor chips...
9024403 Image sensor package  
An image sensor package and image sensor chip capable of being slenderized while enhancing the reliability with respect to physical impact are provided. The image sensor package includes an image...
9024421 Connection arrangement for semiconductor power modules  
A semiconductor power module includes at least two sub modules. The sub modules include at least one respective transistor having a collector, an emitter, and a gate. The module includes a...
9024424 Stacked electronic component and manufacturing method thereof  
A stacked electronic component comprises a first electronic component adhered on a substrate via a first adhesive layer, and a second electronic component adhered by using a second adhesive layer...
9018772 Chip structure and multi-chip stack package  
A chip structure and a multi-chip stack package are provided. The chip structure includes a chip, at least one interlink plate and a plurality of first connection terminals. The chip has an active...
9018969 Semiconductor device with aligned bumps  
In a semiconductor device in which semiconductor chips having a number of signal TSVs are stacked, a huge amount of man-hours have been required to perform a continuity test for each of the signal...
9018773 Chip arrangement and a method for forming a chip arrangement  
A chip arrangement is provided. The chip arrangement includes: a first chip electrically connected to the first chip carrier top side; a second chip electrically connected to the second chip...
9012787 Electronic system for wave soldering  
An electronic board includes conducting traces having an upper surface at least partially sunken with respect to a gluing surface of the board. A surface mount technology electronic device for...
9006905 Semiconductor device with through silicon via and alignment mark  
A semiconductor device with a semiconductor substrate having a first surface and an opposite-facing second surface, a through electrode electrically connected to the semiconductor element and...
9006872 Semiconductor chip package having via hole and semiconductor module thereof  
In one embodiment, a semiconductor chip package includes an insulation frame having an opening part formed in a center thereof and a via hole formed around the opening part; a semiconductor chip...
9006908 Integrated circuit interposer and method of manufacturing the same  
Systems and methods are provided for an interposer for coupling two or more integrated circuit dies to a circuit package. A first integrated circuit portion is disposed on a first location of a...
9006907 Distributed on-chip decoupling apparatus and method using package interconnect  
An integrated circuit device is disclosed. The integrated circuit device includes a semiconductor die fabricated by a front-end semiconductor process and having oppositely disposed planar...
9006889 Flip chip packages with improved thermal performance  
Systems and methods for improving thermal performance, such as thermal dissipation, of flip chip packages that include one or more flip chip dies are disclosed. In some embodiments, a thermal...
9006884 Three dimensional semiconductor device including pads  
A semiconductor device includes a substrate in which a cell region and a contact region are defined, a pad structure including a plurality of first conductive layers and a plurality of first...
RE45463 Stacked microelectronic assemblies with central contacts  
A stacked microelectronic assembly includes a dielectric element and a first and second microelectronic element stacked one on top of the other with the first microelectronic element underlying at...
9000574 Semiconductor device for battery power voltage control  
A voltage generated in any of a plurality of semiconductor chips is supplied to another chip as a power supply voltage to realize a stable operation of a semiconductor device in which the...
9000583 Multiple die in a face down package  
A microelectronic package includes a subassembly including a first substrate and first and second microelectronic elements having contact-bearing faces facing towards oppositely-facing first and...
9000584 Packaged semiconductor device with a molding compound and a method of forming the same  
The mechanisms of forming a molding compound on a semiconductor device substrate to enable fan-out structures in wafer-level packaging (WLP) are provided. The mechanisms involve covering portions...
8994162 Semiconductor multi-package module including tape substrate land grid array package stacked over ball grid array package  
A single metal layer tape substrate includes a patterned metal layer affixed to a patterned dielectric layer. The dielectric layer is patterned to provide openings exposing lands and bond sites on...
8994190 Low-temperature flip chip die attach  
A mechanism for electrically coupling a semiconductor device die to a semiconductor device package substrate that avoids introduction of excessive temperature induced stresses to the semiconductor...
8994163 Semiconductor assemblies, stacked semiconductor devices, and methods of manufacturing semiconductor assemblies and stacked semiconductor devices  
Stacked semiconductor devices, semiconductor assemblies, methods of manufacturing stacked semiconductor devices, and methods of manufacturing semiconductor assemblies. One embodiment of a...
8994161 Semiconductor device package and methods for producing same  
Some embodiments have a semiconductor chip supported above a substrate, a filler layer encapsulating the semiconductor chip, a heat sink; and through contacts extending upwardly from the substrate...
8994192 Integrated circuit packaging system with perimeter antiwarpage structure and method of manufacture thereof  
A method of manufacture of an integrated circuit packaging system comprising: providing a package carrier; mounting an integrated circuit to the package carrier; and forming a perimeter...
8994184 Semiconductor device and method of forming interposer and opposing build-up interconnect structure with connecting conductive TMV for electrical interconnect of FO-WLCSP  
A semiconductor device has a substrate with a plurality of conductive vias and conductive layer formed over the substrate. A semiconductor die is mounted over a carrier. The substrate is mounted...
8994150 Systems and methods for lowering interconnect capacitance  
Methods and apparatus for lowering the capacitance of an interconnect, are disclosed. An example apparatus may include an interconnect formed in at least one integrated circuit and configured to...
8994191 Die-die stacking structure and method for making the same  
The present invention relates to die-die stacking structure and the method for making the same. The die-die stacking structure comprises a top die having a bottom surface, a first insulation layer...
8987052 Attachment of microelectronic components  
Sub-micron precision alignment between two microelectronic components can be achieved by applying energy to incite an exothermic reaction in alternating thin film reactive layers between the two...
8987833 Stacked composite device including a group III-V transistor and a group IV lateral transistor  
In one implementation, a stacked composite device comprises a group IV lateral transistor and a group III-V transistor stacked over the group IV lateral transistor. A drain of the group IV lateral...
8987066 Processing unit comprising integrated circuits including a common configuration of electrical interconnects  
A processing unit comprises a plurality of individual integrated circuits (ICs) electrically connected to one another via a common configuration of electrical interconnects (e.g., through-silicon...