Matches 351 - 400 out of 621 < 1 2 3 4 5 6 7 8 9 10 11 12 13 >
Match Document Document Title
6049120 Thermal-stress-resistant semiconductor sensor  
A semiconductor sensor is provided with a good temperature characteristic, the sensor being capable of preventing a pressure or acceleration detection characteristic from being affected by a change...
6040621 Semiconductor device and wiring body  
A semiconductor device is provided with a wiring body including an insulating supporting substrate, and signal lines, power lines and ground lines printed on first and second surfaces of the...
6034436 Semiconductor device having an improved through-hole structure  
A semiconductor device has isolated first layer interconnects, second layer interconnects, third layer interconnects, and through-holes each connecting one of the second layer interconnects and a...
6031289 Integrated circuit which uses a recessed local conductor for producing staggered interconnect lines  
An improved multilevel interconnect structure is provided. The interconnect structure includes several levels of conductors, wherein conductors on one level are staggered with respect to conductors...
6005265 Semiconductor integrated circuit device having wiring layout for small amplitude signals  
A semiconductor integrated circuit device capable of reducing delay of wiring as far as possible is provided. The semiconductor integrated circuit device comprises at least two sets of pairs of...
5998872 Semiconductor device for avoiding cracks in insulating spaces between metal wiring patterns  
A semiconductor device having a metal layer pattern which prevents cracks from forming in insulating spaces. The semiconductor device includes a plurality of metal layers stacked vertically and a...
5994781 Semiconductor chip package with dual layer terminal and lead structure  
An assembly for packaging a microchip has a dielectric element including a top dielectric layer having a bottom surface. Traces extend at the bottom surface to connect terminals of the dielectric...
5990561 Tungsten plugs for integrated circuits and methods for making same  
A method for producing a glue layer for an integrated circuit which uses tungsten plugs in accordance with the present invention includes: (A) providing a substrate which has a surface, a center,...
5982039 Completely buried contact holes  
A method for forming a completely buried contact hole and a semiconductor device having a completely buried contact hole in an interconnection structure is disclosed. The completely buried contact...
5977639 Metal staples to prevent interlayer delamination  
The present invention provides in one embodiment thereof an integrated circuit (IC) that includes silicon substrate. The integrated circuit includes a plurality of dielectric and metal layers...
5973376 Architecture having diamond shaped or parallelogram shaped cells  
Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two...
5955778 Lead frame with notched lead ends  
A lead frames has a forked top portion which has a recessed portion adjusted for receipt of a wire so that the wire is so caught by the forked top portion as to prevent the wire from being largely...
5955704 Optimal PWA high density routing to minimize EMI substrate coupling in a computer system  
A computer system includes a multi-layer circuit board having first and second routing layers. A component including pads is mounted on the first layer. Crosstalk protection is provided by a...
5955788 Semiconductor device having multilevel wiring with improved planarity  
A semiconductor device having metal wirings in two or more layers has a slit formed in the metal wiring which is a lower layer, and a SOG film flows into the slit while forming the SOG film. The...
5949144 Pre-bond cavity air bridge  
A handle wafer has a cavity coated with a dielectric. A device wafer is bonded to the handle wafer. Metal lines, devices or circuits fabricated on device layer overlay the cavity in the handle...
5945740 Semiconductor device  
A semiconductor device comprising a lower level pattern formed on a semiconductor substrate, an interlayer insulator film covering the lower level pattern, and an upper level pattern formed on the...
5945709 Integrated circuit die having thick bus to reduce distributed resistance  
To reduce the distributed resistance in an integrated circuit die, a relatively thick metal strap layer is deposited on a bus or other conductive path in the top metal layer. The metal strap layer...
5939791 Electrically conductive interconnects for integrated circuits  
A sharp transition or step is first formed on the surface of a semiconductor material. A layer of interconnect metal is deposited by conformal CVD and substantially the same thickness of the metal...
5929528 Semiconductor device and method of manufacturing the same  
The semiconductor of this invention is provided with a first inter-layer insulating film formed on the surface of a semiconductor substrate to a first film thickness; a plurality of first wiring...
5905307 Semiconductor device incorporating multilayer wiring structure  
In a semiconductor device having multilayer wiring, upper metallization layers and elements or lower metallization layers are eletrically connected via embedded metals in contact holes or through...
5903057 Semiconductor device that compensates for package induced delay  
A semiconductor device includes a first and second pin, a first lead finger coupled to the first pin and a second lead finger coupled to the second pin, and a die coupled to the lead fingers. The...
5894170 Wiring layer in semiconductor device  
A semiconductor device includes (a) a semiconductor substrate, (b) a first interlayer insulating film formed on the semiconductor substrate, (c) a wiring layer having a thickness T and a width W1...
5889329 Tri-directional interconnect architecture for SRAM  
Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two...
5886410 Interconnect structure with hard mask and low dielectric constant materials  
An interconnect system is provided. The interconnect system includes a silicon substrate and a first dielectric layer formed upon the silicon substrate. The interconnect system also includes a...
5883416 Gate-contact structure to prevent contact metal penetration through gate layer without affecting breakdown voltage  
The present invention discloses a power transistor disposed on a substrate. The power device includes a core cell area comprising a plurality of power transistor cells each having drain and a...
5880528 Energy absorbing structures to prevent damage to an integrated circuit  
The present invention provides in one embodiment thereof an integrated circuit (IC). The IC includes a silicon substrate and a dielectric layer formed upon the silicon substrate. The IC further...
5874778 Embedded power and ground plane structure  
A device architecture with embedded planar conductive ground and power planes in the device architecture. The apparatus includes a first conductive plane, a second conductive plane, a signal plane...
5869867 FET semiconductor integrated circuit device having a planar element structure  
In a semiconductor device, an extra wiring area generated by the connection of an upper layer wiring to an element on a semiconductor substrate is reduced to improve the level of integration, and...
5866924 Method and apparatus for routing a clock tree in an integrated circuit package  
A method and apparatus for routing a clock tree in an integrated circuit device. Prior art clock trees were routed entirely on an integrated circuit device, thereby increasing the size, complexity,...
5861676 Method of forming robust interconnect and contact structures in a semiconductor and/or integrated circuit  
A conducting trench in a dielectric layer can function as both (a) a plurality of contacts and (b) an interconnect in a semiconductor device. The conducting trench may be made by depositing a...
5838072 Intrachip power distribution package and method for semiconductors having a supply node electrically interconnected with one or more intermediate nodes  
An integrated circuit has a supply node for supplying power to at least one intermediate node coupled to circuitry for receiving power. Rather than transmit power from the supply node to the...
5838546 Mounting structure for a semiconductor circuit  
In a tape carrier package applying a TAB technique, a flex rigid PWB is used as a tape carrier. A flexible portion is provided with a semiconductor connection terminal. An LSI is directly mounted...
5828121 Multi-level conduction structure for VLSI circuits  
This invention deals with the formation of the multi-level electrode metal structure and the interconnecting inter-level metal studs used in the fabrication of VLSI circuits. After the metal layers...
5821624 Semiconductor device assembly techniques using preformed planar structures  
An interposer (preformed planar structure) is disposed between a die and a substrate (which may be another die). Through holes in the interposer facilitate controlled formation of electrical...
5811882 On-chip shielding coaxial conductors for mixed-signal IC  
In an integrated circuit, capacitively coupled interference (digital-switching or analog cross-talk) is prevented by constructing shielded coaxial conductors for the analog signals. The coaxial...
5812031 Ring oscillator having logic gates interconnected by spiral signal lines  
A ring oscillator circuit of one aspect includes a plurality of logic gates connected in cascade in a ring form and a plurality of signal lines each disposed between adjacent ones of the plurality...
5804854 Memory cell array  
The memory cell array of the present invention has a plurality of memory cell, four memory cells hold a junction region in common. In the each memory cell, a portion of the tunnel oxide layer...
5804871 Lead on chip semiconductor device having bus bars and crossing leads  
Along the column of bonding pad (1), bidding terminal portions (2c), (3c), (4a), (5a) of bus bars (2), (3), and signal lines (4), (5) are arranged; principal wiring portions (2a), (3a) are made to...
5801394 Structure for wiring reliability evaluation test and semiconductor device having the same  
A test line (12) is formed between a pair of current sypplying terminals (11). A step pattern (14) composed of polysilicon or the like is formed below the test line (12) through an inter-layer...
5793114 Self-aligned method for forming contact with zero offset to gate  
A method and structure for self-aligned zero-margin contacts to active and poly-1, using silicon nitride (or another dielectric material with low reflectivity and etch selectivity to oxide) for an...
5789797 Semiconductor device that suppresses electromagnetic noise  
An improved on-chip type filter for filtrating electromagnetic noise is disclosed. Within a sensor chip are provided processing and amplifying circuits, a ground pad, a power pad and an output pad....
5767546 Laternal power mosfet having metal strap layer to reduce distributed resistance  
To reduce the distributed resistance in an integrated circuit die, a relatively thick metal strap layer is deposited on a bus or other conductive path in the top metal layer. The metal strap layer...
5764497 Circuit board connection method and connection structure  
The circuit board connecting method and a connection structure. A first flexible board is adhered to a first surface of the circuit board at a first temperature, and then a second flexible board is...
5761028 Transistor connection assembly having IGBT (X) cross ties  
A hybrid vehicle includes a power unit communicating power between a turbine alternator, flywheel and traction motor. The power unit stores DC power in capacitors and places the power on DC bus for...
5757079 Method for repairing defective electrical connections on multi-layer thin film (MLTF) electronic packages and the resulting MLTF structure  
A multi-layer thin film structure having defined repair lines thereon and a method for repairing interconnections in the multi-layer thin film structure (MLTF) and/or making engineering charges...
5753970 System having semiconductor die mounted in die-receiving area having different shape than die  
Electronic systems utilizing a plurality of integrated circuit packages having at least some large gaps between edges of a semiconductor die and the inner ends of package conductors defining a...
5751057 Lead on chip lead frame design without jumpover wiring  
Lead On Chip ("LOC") leadframe designs for thin, small-outline packages having improved configurations of leadframe members are provided. The LOC leadframes comprise a bus bar, having at least one...
5748550 Multiple power line arrangement for a semiconductor memory device  
A method and system for arranging power lines of a semiconductor memory device in order to prevent cracking of the power lines and to reduce resistance of the power lines without the provision of...
5747867 Integrated circuit structure with interconnect formed along walls of silicon island  
Insulating trenches (2) in the silicon layer of an SOI substrate that extend onto the insulating layer of the SOI substrate define silicon islands (3). At least one of the silicon islands (3) is an...
5734187 Memory cell design with vertically stacked crossovers  
A memory cell with vertically stacked crossovers. In prior memory cells, crossover connections within the memory cell were implemented in the same device layer. This wasted valuable design space,...
Matches 351 - 400 out of 621 < 1 2 3 4 5 6 7 8 9 10 11 12 13 >