Matches 301 - 350 out of 621 < 1 2 3 4 5 6 7 8 9 10 11 12 13 >
Match Document Document Title
6404056 Semiconductor integrated circuit  
On transistors P 1 , P 2 , N 1 and N 2 constituting an NAND gate, a interconnection pattern W of metal having high melting point and aluminum interconnection patterns Al 1 and Al 2 are stacked....
6396146 Semiconductor device and its manufacturing method  
Dummy patterns are formed in signal patterns of a first metal layer, an insulating film covering such patterns is flattened by CMP, and only dummy patterns are selectively etched by anisotropic...
6362524 Edge seal ring for copper damascene process and method for fabrication thereof  
A metal edge seal ring is formed in a trench made up of a large number of short, connected legs in perpendicular relation. Metal is deposited in the trench, and because the metal is comprised of...
6355977 Semiconductor chip or device having a connecting member formed on a surface protective film  
A semiconductor chip which is joined to a surface of a solid such as a semiconductor chip or a wiring board. The semiconductor chip includes a surface protective film formed on its surface opposite...
6331736 Utilization of die repattern layers for die internal connections  
The formation of routing traces on an external surface of a semiconductor device, such as a flip-chip, which has a plurality of ball or bump sites patterned in specific locations, wherein the ball...
6329720 Tungsten local interconnect for silicon integrated circuit structures, and method of making same  
A local interconnect for an integrated circuit structure is described capable of bridging over a conductive element to electrically connect together, at the local interconnect level, non-adjacent...
6326693 Semiconductor integrated circuit device  
A semiconductor integrated circuit device has core circuits having rectangular shapes in plan view and power lines surronding the core circuit to connect the cores with an external power supply....
6326695 Twisted bit line structures and method for making same  
A twisted bit line structure (69) in an integrated memory circuit, and method for making it are presented. The structure is constructed by forming bit line traces (70-73) on an integrated circuit...
6313526 Semiconductor apparatus, Including thin film belt-like insulating tape  
A semiconductor apparatus includes a thin film belt-like insulating tape having a plurality of predetermined wire patterns thereon, and a plurality of IC chips that are provided on a surface of the...
6310399 Semiconductor memory configuration with a bit-line twist  
A semiconductor memory configuration includes bit lines in a bit-line plane, a further plane different from the bit-line plane, word lines, and a memory cell area adjacent the bit-line plane, some...
6310402 Semiconductor die having input/output cells and contact pads in the periphery of a substrate  
The width of an input/output forming region is matched with the minimum width adoptable as a layout interval between pads in advance. Pads corresponding to (least common multiple)รท(layout interval...
6307263 Integrated semiconductor chip with modular dummy structures  
For an integrated semiconductor chip to operate reliably, it is necessary to homogenize a substrate potential as far as possible in all regions of the chip. In order to improve the substrate...
6282113 Four F-squared gapless dual layer bitline DRAM array architecture  
A semiconductor device having a compact folded bitline architecture. Bitlines for a memory cell array arranged into bitline pairs constituting, when in use, a selected bitline and its complement....
6281586 Integrated semiconductor circuit configuration having stabilized conductor tracks  
An integrated semiconductor circuit configuration includes stabilized conductor tracks which run in different planes. Critical locations of the conductor tracks which are dictated by the layout are...
6278186 Parasitic current barriers  
In one embodiment a substrate 14 is patterned to have high and low conductive areas 110, 112, respectively. Metal lines 104, 108 in dielectric layer 16 pass transversely over the areas 110, 112....
6274936 Method for forming a contact during the formation of a semiconductor device  
A method for forming a semiconductor device comprises the steps of forming first and second conductive lines having a space therebetween over a substrate, said first and second conductive lines...
6261883 Semiconductor integrated circuit device, and fabrication process and designing method thereof  
Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a...
6259162 Method for reducing capactive coupling between conductive lines  
An embodiment of the present invention discloses a memory device having an array with digit lines arranged in complementary pairs, the array comprising; a substantially planar layer having trenches...
6246118 Low dielectric semiconductor device with rigid, conductively lined interconnection system  
Multi-level semiconductor devices are formed with reduced parasitic capacitance without sacrificing structural integrity or electromigration performance by removing the inter-layer dielectrics and...
6245653 Method of filling an opening in an insulating layer  
The present invention is about a method for filling an opening in an insulating layer in a fast and highly reliable way and can be used to fill openings such as trenches and via holes...
6246121 High performance flip-chip semiconductor device  
A flip-chip semiconductor device with generic bump patterns formed on a semiconductor substrate and having optimized electrical performance is provided. In a preferred embodiment, the flip-chip...
6225646 Integrated circuit incorporating a memory cell and a transistor elevated above an insulating base  
An integrated circuit is presented. The integrated circuit may include a memory cell formed above an insulating base. The insulating base may either be arranged above a substrate or serve as a...
6222274 Bonding wire loop shape for a semiconductor device  
A semiconductor device with wires mounted thereon, each one of the wires, which connects a first bonding point and a second bonding point which are positioned substantially in a lateral...
6211572 Semiconductor chip package with fan-in leads  
A compliant semiconductor chip package with fan-in leads and a method for manufacturing the same. The package, or "assembly", contains a multiplicity of bond ribbons connected between the contacts...
6207986 Semiconductor integrated circuit device  
A semiconductor integrated circuit device offering a phase pattern makeup that excludes mixture of insular and linear patterns in a mask for forming a single wire electrode layer so as to eliminate...
6205044 Decoder connection configuration for memory chips with long bit lines  
A decoder connection configuration for memory chips, in which, in a dummy region of a decoder, the dummy region being caused by a bit line twist, additional plated-through holes are provided...
6194777 Leadframes with selective palladium plating  
A leadframe having the desirable features of palladium plated leadframes, such as compatibility with both wire bonding and solder reflow, as well as good adhesion to molding compounds is provided...
6194786 Integrated circuit package providing bond wire clearance over intervening conductive regions  
An integrated circuit in a package having a ground and/or power ring and bond wires crossing the ground and/or power ring, the bond wires further coupled to signal traces. A semiconductor...
6191486 Technique for producing interconnecting conductive links  
Conductive links are provided between conductive materials, e.g., metals, separated by a non-conductive material, e.g., a silicon based glass material. In a preferred embodiment a single pulse of...
6181014 Integrated circuit memory devices having highly integrated SOI memory cells therein  
Integrated circuit memory devices having highly integrated SOI memory cells therein include an SOI substrate having a semiconductor active layer therein. A first trench isolation region is also...
6177732 Multi-layer organic land grid array to minimize via inductance  
The present invention is a method and apparatus to minimize via inductance in a multi-layer organic land grid array (OLGA) packaging. A plurality of layers are staggered vertically. The plurality...
6169331 Apparatus for electrically coupling bond pads of a microelectronic device  
A method and apparatus for electrically coupling bond pads on the surface of a microelectronic device. The apparatus can include a microelectronic device having at least two bond pads with a...
6160715 Translator for recessed flip-chip package  
The specification describes a recessed chip IC package in which the IC chip is bonded to a translator, and power and ground planes for IC power and ground interconnections are formed on separate...
6160297 Semiconductor memory device having a first source line arranged between a memory cell string and bit lines in the direction crossing the bit lines and a second source line arranged in parallel to the bit lines  
A semiconductor device comprises select gates and control gates of a plurality of memory cells therebetween so that gate members on upper portions of stacked gates may cross element regions. A...
6160316 Integrated circuit utilizing an air gap to reduce capacitance between adjacent metal linewidths  
A method is provided for forming a multi-level interconnect in which capacitive coupling between laterally adjacent conductors employed by an integrated circuit is reduced. According to an...
6150721 Integrated circuit which uses a damascene process for producing staggered interconnect lines  
An improved multilevel interconnect structure is provided. The interconnect structure includes several levels of conductors, wherein conductors on one level are staggered with respect to conductors...
6147403 Semiconductor body with metallizing on the back side  
To markedly reduce wafer warping of semiconductor wafers without weakening the strength of adhesion to substrate materials, a novel back side metallizing system is presented. On a silicon...
6147410 Electronic component and method of manufacture  
An electronic component includes a semiconductor substrate (101, 301, 401), an electrically conductive layer (102, 103, 302, 303, 402, 403) supported by the semiconductor substrate (101, 301, 401),...
6147361 Polysilicon electromigration sensor which can detect and monitor electromigration in composite metal lines on integrated circuit structures with improved sensitivity  
A polysilicon sensor is described which can be incorporated onto a silicon wafer containing integrated circuits for the purpose of detecting and monitoring electromigration(EM) in metal test...
6140704 Integrated circuit memory devices with improved twisted bit-line structures  
An integrated circuit memory device includes a memory cell array and first and second sense amplifiers positioned on respective opposite first and second sides of the memory cell array. A first bit...
6137182 Method of reducing via and contact dimensions beyond photolithography equipment limits  
A semiconductor process for forming an interlevel contact. A semiconductor wafer is provided with a semiconductor substrate, a first conductive layer formed on the substrate, and a dielectric layer...
6133144 Self aligned dual damascene process and structure with low parasitic capacitance  
An improved and novel process for fabricating unique interconnect conducting lines and via contact structures has been developed. Using this special self aligned dual damascene process, special...
RE36837 Structure of contact between wiring layers in semiconductor integrated circuit device  
An insulation film is interposed between a first-level wiring layer and a second-level wiring layer. A contact hole is formed in the insulation film on the first-level wiring layer to electrically...
6097098 Die interconnections using intermediate connection elements secured to the die face  
A semiconductor device, such as an integrated circuit die, includes a plurality of bond pads on an active surface thereof electrically connected to internal circuitry of the semiconductor device,...
6097073 Triangular semiconductor or gate  
Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two...
6087721 Semiconductor device with a high-frequency bipolar transistor on an insulating substrate  
A bipolar transistor (3) is provided with a first main surface (4) in contact with a conductive mounting surface (2), and with an opposed second main surface (12) having connection pads (5, 6, 40)...
6084303 Integrated circuit comprising connection pads emerging on one surface  
The printed circuit has connection pads emerging in a face of the integrated circuit, which face is covered in an insulating layer (5) having openings in register with the connection pads, and at...
6084306 Bridging method of interconnects for integrated circuit packages  
An integrated circuit package (30) having first and second layers (76, 78), a plurality of routing pads (82) being integral with the first layer (76), a plurality of upper and lower conduits (18,...
6072213 Transistor having an etchant-scalable channel length and method of making same  
An integrated circuit fabrication process is provided for forming a transistor having an ultra short channel length. First and second masks are formed upon a conductive gate layer, wherein the...
6051889 Semiconductor device having a flip-chip structure  
A semiconductor device includes a substrate having a first principal surface carrying thereon a first wiring pattern and a semiconductor chip having a second principal surface carrying a second...
Matches 301 - 350 out of 621 < 1 2 3 4 5 6 7 8 9 10 11 12 13 >