Matches 251 - 300 out of 621 < 1 2 3 4 5 6 7 8 9 10 11 12 13 >
Match Document Document Title
6680536 Probe unit having resilient metal leads  
A probe unit has a plurality of metal leads regularly juxtaposed on the surface of a substrate. Each metal lead has a resilient contact piece in a front portion of the lead, the resilient contact...
6680543 Semiconductor integrated circuit and system  
A semiconductor integrated circuit 10 includes a semiconductor substrate 1 , an insulating layer 2 formed on the semiconductor substrate 1 , and a bonding pad 3 formed on the insulating...
6674176 Wire bond package with core ring formed over I/O cells  
A wire bond package for an integrated circuit die includes a first I/O core ring and a second I/O core ring formed in a first metal layer; a pad strap formed in a second metal layer overlapping the...
6670710 Semiconductor device having multi-layered wiring  
A semiconductor device is provided with a first insulating film, a first wiring layer formed in the first insulating film, a second insulating film formed above the first wiring layer and the first...
6664641 Wiring structure for an integrated circuit  
A wire width and a wiring space of each of signal wires 1 and ground/power wires 2 are determined to be a wire width W 1 (the minimum wire width) and a wiring space S 1 , respectively. A wire...
6657307 Semiconductor integrated circuit having functional macro with improved power line connection structure  
In a semiconductor integrated circuit having a functional macro, plural first and second power lines extending over the functional macro and supplying first-level and second-level voltages...
6657870 Die power distribution system  
A power distribution system for distributing external power across a die is disclosed, wherein the die has horizontal and vertical centerlines. The system and method include providing a power mesh...
6650015 Cavity-down ball grid array package with semiconductor chip solder ball  
A cavity-down ball grid array package includes a substrate having a through cavity provided therein. A heat sink is attached to the substrate and a semiconductor chip in the cavity is attached to...
6639322 Flip-chip transition interface structure  
A flip-chip transition interface structure is suitable for use in high speed applications that require low return losses. The transition interface includes a conductive signal element and two...
6635960 Angled edge connections for multichip structures  
A multichip module that utilizes an angled interconnect to electrically interconnect chips in the module that are positioned at an angle relative to each other. The multichip module may comprise a...
6633057 Non-volatile semiconductor memory and fabricating method therefor  
In a non-volatile semiconductor memory having a peripheral circuit zone and a memory zone including plural memory cells each having a floating gate and a control gate, an interlayer insulator is...
6624500 Thin-film electronic component and motherboard  
An object of the invention is to provide a thin-film electronic component and a motherboard in which coupling strength of an external terminal to a supporting substrate is improved. The thin-film...
6621171 Semiconductor device having a wire laid between pads  
It is intended to lower an increase of an area of an unused area or a wiring area, which is caused due to addition or enhancement of a particular function of a semiconductor device without...
6614049 System LSI chip having a logic part and a memory part  
A dummy pattern layer, which has not been effectively used, included in upper wire layers of a memory part of a system LSI chip is utilized as a large-scale wire TEG (test element group) region...
6611039 Vertically oriented nano-fuse and nano-resistor circuit elements  
Vertically oriented nano-circuits including fuses and resistors allow for significant densities to be achieved. The vertically oriented nano-circuits can be fabricated using standard known...
6611062 Twisted wordline strapping arrangement  
A high density wordline strapping arrangement is obtained by routing three primary metal- 2 wordline straps in the same space as four polysilicon wordline, and routing the fourth wordline strap in...
6594173 Method for digit line architecture for dynamic memory  
A novel bi-level DRAM architecture is described which achieves significant reductions in die size while maintaining the noise performance of traditional folded architectures. Die size reduction...
6570258 Method for reducing capacitive coupling between conductive lines  
An embodiment of the present invention discloses a memory device having an array with digit lines arranged in complementary pairs, the array comprising; a substantially planar layer having trenches...
6559544 Programmable interconnect for semiconductor devices  
A structure for selectively programming interconnections between an input contact and an output contact segment in a multilayer semiconductor, comprising a first group of metal segments each being...
6555922 IC bonding pad combined with mark or monitor  
A semiconductor device includes a bonding pad formed on a substrate and a mark region formed on the substrate right underneath the bonding pad, such that the mark region is covered by the bonding pad.
6548839 LDMOS transistor structure using a drain ring with a checkerboard pattern for improved hot carrier reliability  
An LDMOS array includes an array of alternating source regions and drain regions formed in a semiconductor substrate to define a checkerboard pattern of source and drain regions. A source contact...
6548907 Semiconductor device having a matrix array of contacts and a fabrication process thereof  
A semiconductor device includes a semiconductor chip carrying a plurality of contact electrodes on a principal surface thereof, wherein the contact electrodes are arranged symmetrically about an...
6545348 Package for a semiconductor device comprising a plurality of interconnection patterns around a semiconductor chip  
A first interconnection pattern having a comb shape is formed around a semiconductor chip on a package body. A second interconnection pattern having a comb shape is formed around the first...
6541850 Utilization of die active surfaces for laterally extending die internal and external connections  
The formation of routing traces on an external surface of a semiconductor device, such as a flip-chip, which has a plurality of ball or bump sites patterned in specific locations, wherein the ball...
6541853 Electrically conductive path through a dielectric material  
A structure and method thereof for providing an electrically conductive path between a first conductive point and a second conductive point. The structure includes an insulating material disposed...
6541869 Scalable data processing apparatus  
In a scalable data processing apparatus, particularly a data storage apparatus, one or more thin-film devices which form a substantially planar layer comprise a plurality of sublayers of thin film....
6541868 Interconnecting conductive links  
Conductive links are provided between conductive materials, e.g., metals, separated by a non-conductive material, e.g., a silicon based glass material. In a preferred embodiment a single pulse of...
6541867 Microelectronic connector with planar elastomer sockets  
A component for mounting semiconductor chips or other microelectronic units includes a compliant, sheet-like body with arrays of sheet-like conductive pads on upper and lower surfaces of the body....
6528871 Structure and method for mounting semiconductor devices  
A structure and method of mounting semiconductor devices which can cope with miniaturization and high-speed transmission by embedding a semiconductor device within a wiring layer or transmission...
6504244 Semiconductor device and semiconductor module using the same  
A semiconductor device of the present invention is made up of a semiconductor chip and a single wiring tape resembling a film carrier and including a wiring layer that has a preselected pattern....
6504246 Integrated circuit having a balanced twist for differential signal lines  
A balanced twist design for differential small signal pairs which is balanced in terms of resistance, capacitance and process variance. In the twist design of the present invention, each routing (...
6504255 Digit line architecture for dynamic memory  
A novel bi-level DRAM architecture is described which achieves significant reductions in die size while maintaining the noise performance of traditional folded architectures. Die size reduction...
6500706 Bit-line interconnection scheme for eliminating coupling noise in stack DRAM cell with capacitor under bit-line (CUB) in stand-alone or embedded DRAM  
A method for forming a stack DRAM cell with CUB wherein coupling noise is eliminated is described. Bit-lines are formed according to one of three methods. In a first method, a first pair of...
6486412 Wiring board, method for producing same, display device, and electronic device  
In a wiring board having a mounting region on which an integrated circuit having a plurality of terminals is mounted, and having a plurality of substrate-side wiring lines to be connected to the...
6483714 Multilayered wiring board  
A multilayered wiring board comprising a first stacked structure consisting essentially of a first insulating layer having a first parallel conductor array and a second insulating layer formed...
6483368 Addressable diode isolated thin film cell array  
An address element, including a polysilicon resistor functioning as a heating element and blocking diode preventing sneak current to unaddressed elements, is selectively addressed using row and...
6476506 Packaged semiconductor with multiple rows of bond pads and method therefor  
A semiconductor die has three rows or more of bond pads with minimum pitch. The die is mounted on a package substrate having three rows or more of bond fingers and/or conductive rings. The bond...
6472764 Method and apparatus for implementing selected functionality on an integrated circuit device  
A semiconductor device is disclosed that includes a die having an active surface bearing integrated circuitry, the die including a plurality of bond pads thereon at least some of which are...
6472763 Semiconductor device with bumps for pads  
A conductive electrode pad is formed on a partial area of an insulating surface. An insulating film covers the electrode pad. The insulating film has an opening exposing at least a partial upper...
6465891 Integrated-circuit package with a quick-to-count finger layout design on substrate  
An integrated-circuit package with a quick-to-count finger layout design on substrate is proposed, which can help fabrication engineers to visually check the total number of fingers on the...
6459136 Single metal programmability in a customizable integrated circuit device  
A customizable integrated circuit including a plurality of electrically conducting routing layers formed on a substrate for interconnecting a plurality of logic units formed on the substrate,...
6458623 Conductive adhesive interconnection with insulating polymer carrier  
A method and apparatus is provided for forming an electronic assembly whereby an insulating polymer matrix having a plurality of conductor holes is attached to a first substrate wherein the...
6452260 Electrical interface to integrated circuit device having high density I/O count  
A method of and an apparatus for electrically interconnecting two integrated circuits devices includes mounting the two devices face to face. A first device is mounted for example to a substrate or...
6448663 Semiconductor device, semiconductor device mounting structure, liquid crystal device, and electronic apparatus  
A semiconductor device, a mounting structure thereof, a liquid crystal device, and an electronic apparatus having an improved bump electrode structure, such that the bump electrodes and...
6441501 Wire-bonded semiconductor device with improved wire arrangement scheme for minimizing abnormal wire sweep  
A wire-bonded semiconductor device with an improved wire-arrangement scheme is proposed, which can help minimize abnormal wire sweep during encapsulation process. Among the bonding wires on the...
6429522 Microprocessor having air as a dielectric and encapsulated lines  
A multi-layer semiconductor circuit comprising a plurality of conductive lines having air as a dielectric between the sides of the conductive lines in a first layer and having a structurally...
6424035 Semiconductor bilateral switch  
A semiconductor bilateral switch that minimizes the on-state resistance by making a common-source connection between the switch transistors internal to the package. Wire bonds internally connecting...
6407460 Multilayer circuit board  
The present invention provides a multilayer circuit board for mounting thereon a semiconductor chip or other electronic elements having electrode terminals or other connection terminals which are...
6407455 Local interconnect using spacer-masked contact etch  
A semiconductor device including a structure having an upper surface and an contact surface formed at the upper surface of the structure. An insulating material is formed over the contact surface...
6407434 Hexagonal architecture  
Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two...
Matches 251 - 300 out of 621 < 1 2 3 4 5 6 7 8 9 10 11 12 13 >