Matches 451 - 500 out of 1963 < 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 >
Match Document Document Title
7211850 Semiconductor device with specifically shaped contact holes  
An interlayer insulating film covering a ferroelectric capacitor is formed, and through the interlayer insulating film, contact holes each reaching a capacitor electrode are formed. A wiring...
7211897 Semiconductor device and method for fabricating the same  
The semiconductor device comprises on a semiconductor substrate an insulating structure formed of a plurality of insulating films; an interconnection structure buried in the insulating structure...
7211896 Semiconductor device and method of manufacturing the same  
There is provided a method of manufacturing a semiconductor device in which interconnect capacitance is restrained. The semiconductor device 200 comprises a semiconductor substrate; a second...
7211899 Circuit substrate and method for fabricating the same  
A circuit substrate comprises a glass substrate 16 , through-holes 18 formed through the glass substrate 16 and via electrodes 20 buried in the through-holes 18 . An opening width of the...
7208839 Semiconductor component assemblies having interconnects  
Methods relating to forming interconnects through injection of conductive materials, to fabricating semiconductor component assemblies, and to resulting assemblies. A semiconductor component...
7208843 Routing design to minimize electromigration damage to solder bumps  
A novel pad structure for an integrated circuit component that utilizes a bump interconnect for connection to other integrated circuit components that produces a relatively uniform current...
7208838 Semiconductor device, circuit board, and electronic instrument suitable for stacking and having a through hole  
A semiconductor device includes a semiconductor device body section having a substrate and an electrode formed on the substrate. A through-hole is formed through the electrode and the substrate in...
7208348 Methods of fabricating a via-in-pad with off-center geometry  
The electrical contacts, such as ball grid array (BGA) solder balls, of an integrated circuit (IC) are coupled to printed circuit board (PCB) bonding pads that include vias. According to an...
7208828 Semiconductor package with wire bonded stacked dice and multi-layer metal bumps  
A semiconductor package includes a substrate formed of a board material, a semiconductor die bonded to the substrate, and an encapsulant on the die. The package also includes an array of external...
7208831 Semiconductor device having multilayer wiring structure and method, wherein connecting portion and wiring layer are formed of same layer  
A method for manufacturing a semiconductor device includes a step of forming a first groove in a first insulating film, forming a conductive film in the first groove, a step of selectively forming...
7205668 Multi-layer printed circuit board wiring layout  
A multi-layer printed circuit board (PCB) includes a first wire layer, a middle layer above the first wire layer, a second wire layer above the middle layer, and a slanting via formed in the middle...
7205486 Thermally isolated via structure  
This document discusses, among other things, a flexible circuit or other laminate comprising a first conductive layer and a second conductive layer disposed over the first conductive layer. An...
7205613 Insulating substrate for IC packages having integral ESD protection  
An IC package substrate having integral ESD protection features and elements and a method for construction of the same are disclosed
7205649 Ball grid array copper balancing  
A ball grid array device includes a substrate having a first major surface and a second major surface. The first major surface includes leads for electrical connections. The second major surface is...
7202566 Crossed power strapped layout for full CMOS circuit design  
An integrated circuit device and method thereof includes a substrate and a plurality of microelectronic devices. Each of the microelectronics devices includes a patterned feature located over the...
7202556 Semiconductor package having substrate with multi-layer metal bumps  
A semiconductor package includes a substrate formed of a board material, a semiconductor die bonded to the substrate, and an encapsulant on the die. The package also includes an array of external...
7202567 Semiconductor device and manufacturing method for the same  
A lower interconnection is provided on a semiconductor substrate. A MIM capacitive element is provided on a first interlayer insulation film in which the lower interconnection is buried, and...
7199473 Integrated low-k hard mask  
Embodiments of the invention provide a device with a hard mask layer between first and second ILD layers. The hard mask layer may have a k value approximately equal to the first and/or second ILD...
7196423 Interconnect structure with dielectric barrier and fabrication method thereof  
An interconnect structure with dielectric barrier and fabrication thereof. The interconnect structure includes a semiconductor substrate and a plurality of stacked structures formed thereon, each...
7193327 Barrier structure for semiconductor devices  
An opening in a dielectric layer having a unique barrier layer structure is provided. In an embodiment, the opening is a via and a trench. The barrier layer, which may comprise one or more barrier...
7190074 Reconstructed semiconductor wafers including alignment droplets contacting alignment vias  
Apparatus, systems and methods relating to the reconstruction of semiconductor wafers for wafer-level processing are disclosed. Selected semiconductor dice having alignment cavities formed in a...
7190077 Semiconductor structure integrated under a pad  
An integrated semiconductor structure has a substrate, a semiconductor element located on the substrate, a pad metal, metal layers located between the pad metal and the substrate, and insulation...
7190078 Interlocking via for package via integrity  
A method of forming an interconnection structure in a microelectronic package, and an interconnection structure of a microelectronic package formed according to the method. The method includes:...
7190080 Semiconductor chip assembly with embedded metal pillar  
A semiconductor chip assembly includes a semiconductor chip that includes a conductive pad, a conductive trace that includes a routing line and a pillar, a connection joint that electrically...
7190079 Selective capping of copper wiring  
Patterned copper structures are fabricated by selectively capping the copper employing selective etching and/or selective electroplating in the presence of a liner material. Apparatus for...
7187084 Damascene method employing composite etch stop layer  
A damascene structure is provided comprising a substrate, a lower intermetal dielectric layer over the substrate, an exposed conductive structure within the lower intermetal dielectric layer, a...
7187080 Semiconductor device with a conductive layer including a copper layer with a dopant  
A method of manufacturing a semiconductor device includes the steps of providing a semiconductor substrate ( 202 ), forming a dielectric layer ( 204 ) over the semiconductor substrate ( 202 ), and...
7187085 Semiconductor device including dual damascene interconnections  
A method (and structure) of forming an interconnect on a semiconductor substrate, includes forming a relatively narrow first structure in a dielectric formed on a semiconductor substrate, forming a...
7183654 Providing a via with an increased via contact area  
An apparatus and method to provide a via with an increased via contact area. A semiconductor support layer is coupled to a dielectric layer and a contact is coupled to the dielectric layer. A via,...
7183653 Via including multiple electrical paths  
A system includes a device having at least one integrated circuit. The integrated circuit further includes a first layer of conductive material, a second layer of conductive material, and a via...
7179733 Method of forming contact holes and electronic device formed thereby  
In a method of forming contact holes without using a vacuum device, a resist film at positions corresponding to contact hole forming regions above a source region 16 , a drain region 18 and a...
7180187 Interlayer connector for preventing delamination of semiconductor device  
An interlayer connector for preventing delamination of semiconductor layers, and methods of forming the connector are disclosed. The connector includes a first connector head in a first distal...
7180180 Stacked device underfill and a method of fabrication  
Numerous embodiments of a stacked device underfill and a method of formation are disclosed. In one embodiment, a method of forming stacked semiconductor device with an underfill comprises forming...
7180191 Semiconductor device and method of manufacturing a semiconductor device  
A semiconductor device 200 comprises a SiCN film 202 formed on a semiconductor substrate (not shown), a first SiOC film 204 formed thereon, a SiCN film 208 formed thereon, a second SiOC...
7180149 Semiconductor package with through-hole  
A semiconductor package of the invention comprises: a semiconductor element provided with a circuit element on one surface of a semiconductor substrate; an external wiring region provided on an...
7180193 Via recess in underlying conductive line  
A semiconductor device includes a dielectric layer, a conductive line, a via, and a via recess in the conductive line. The conductive line is underlying the dielectric layer. The via is formed in...
7180011 Device for minimizing differential pair length mismatch and impedance discontinuities in an integrated circuit package design  
A method of routing an integrated circuit package design includes steps of receiving as input at least a portion of an integrated circuit design including a differential pair of two electrical...
7180170 Lead-free integrated circuit package structure  
An integrated circuit package ( 60 ) has a substrate ( 12 ) with a first surface ( 51 ) for mounting a semiconductor die ( 20 ) and a second surface ( 52 ) defining a via ( 70 ). A lead ( 26 ) is...
7176577 Semiconductor device  
A semiconductor device is made up of a first insulating layer having a through hole; a first interconnection which comprises a first conductive layer, a first barrier layer, and a first main...
7176578 Method for processing a thin film substrate  
The present invention comprises a processed thin film substrate ( 10 ) and a method therefore, in order to produce a flexible printed circuit card, having a plurality of microvias going or passing...
7176533 Semiconductor devices having contact plugs including polysilicon doped with an impurity having a lesser diffusion coefficient than phosphorus  
Forming a semiconductor device can include forming an insulating layer on a semiconductor substrate including a conductive region thereof, wherein the insulating layer has a contact hole therein...
7173339 Semiconductor device having a substrate an undoped silicon oxide structure and an overlaying doped silicon oxide structure with a sidewall terminating at the undoped silicon oxide structure  
An etchant including C 2 H x F y , where x is an integer from two to five, inclusive, where y is an integer from one to four, inclusive, and where x plus y equals six, etches doped silicon dioxide...
7170178 Capacitive integrated circuit structure  
A capacitive structure is provided that includes secondary stacks of superposed secondary electrodes that each include transverse branches connected via a longitudinal branch, means for connecting...
7170182 Semiconductor device with reduced interconnect capacitance  
A semiconductor device has interconnecting lines disposed side by side in a dielectric film. Mutually adjacent pairs of interconnecting lines are separated by a substantially constant distance from...
7170152 Wafer level semiconductor package with build-up layer and method for fabricating the same  
A wafer level semiconductor package with a build-up layer is provided, which includes a glass frame having a through hole for receiving a semiconductor chip therein, a low-modulus buffer material...
7170177 Semiconductor apparatus  
A disclosed semiconductor apparatus includes a substrate, a first insulating layer formed on the substrate, the first insulating layer including a Cu wiring part, and a second insulating layer...
7170174 Contact structure and contact liner process  
A contact structure and a method of forming thereof for semiconductor devices or assemblies are described. The method provides process steps to create a contact structure encompassed by a...
7166923 Semiconductor device, electro-optical unit, and electronic apparatus  
The invention provides a semiconductor device that allows high-scale integration of a pattern layout to reduce the pitch of wiring lines without changing a design rule, and to provide an...
7164206 Structure in a microelectronic device including a bi-layer for a diffusion barrier and an etch-stop layer  
The invention relates to a microelectronic device and a structure therein that includes a diffusion barrier layer having a first thickness and a first dielectric constant. An etch stop layer is...
7161237 Flip chip packaging using recessed interposer terminals  
A method and apparatus for packaging a semiconductor die with an interposer substrate. The semiconductor device assembly includes a conductively bumped semiconductor die and an interposer substrate...
Matches 451 - 500 out of 1963 < 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 >