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9041207 Method to increase I/O density and reduce layer counts in BBUL packages  
An apparatus including a die including a dielectric material on a device side, an insulating layer surrounding a die area and embedding a thickness dimension of the die; and a carrier including a...
9041181 Land grid array package capable of decreasing a height difference between a land and a solder resist  
A land grid array (LGA) package including a substrate having a plurality of lands formed on a first surface of the substrate, a semiconductor chip mounted on a second surface of the substrate, a...
9041206 Interconnect structure and method  
A semiconductor device comprises a first semiconductor chip including a first substrate and a plurality of first metal lines formed over the first substrate and a second semiconductor chip bonded...
9041033 Semiconductor light emitting device  
According to one embodiment, a semiconductor light emitting device includes a first semiconductor layer, a light emitting layer, a second semiconductor layer, a p-side electrode, a plurality of...
9041114 Contact plug penetrating a metallic transistor  
In one embodiment, a semiconductor device includes a semiconductor substrate, and a gate insulator arranged on the semiconductor substrate. The device further includes a gate electrode including a...
9041223 Bump-on-trace (BOT) structures  
A bump-on-trace (BOT) structure is described. The BOT structure includes a first work piece with a metal trace on a surface of the first work piece, wherein the metal trace has a first axis. The...
9041216 Interconnect structure and method of forming the same  
An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower conductive feature in a lower low-k (LK) dielectric layer; a...
9035462 Airgap-containing interconnect structure with patternable low-k material and method of fabricating  
An interconnect structure is provided that includes at least one patterned and cured low-k dielectric material located on a surface of a patterned inorganic antireflective coating that is located...
9034755 Method of epitaxially forming contact structures for semiconductor transistors  
Embodiments of the present invention provide a method of forming contact structure for transistor. The method includes providing a semiconductor substrate having a first and a second gate...
9030021 Printed circuit board having hexagonally aligned bump pads for substrate of semiconductor package, and semiconductor package including the same  
Provided are a printed circuit board (PCB) having hexagonally aligned bump pads as a substrate of a semiconductor package, and a semiconductor package including the same. The PCB includes: a PCB...
9030011 Chip package and method for forming the same  
An embodiment of the invention provides a chip package which includes: a carrier substrate; a semiconductor substrate having an upper surface and a lower surface, disposed overlying the carrier...
9030020 Semiconductor memory device  
In one embodiment, a semiconductor memory device includes a substrate, and device regions formed in the substrate to extend in a first direction which is parallel to a principal plane of the...
9030022 Packages and methods for forming the same  
A device includes a package component having conductive features on a top surface, and a polymer region molded over the top surface of the first package component. A plurality of openings extends...
9029997 Stacked layer type semiconductor device and semiconductor system including the same  
A stacked layer type semiconductor device includes N memories each including at least one main via and (N−1) sub vias, the N memories being sequentially stacked on one-another so that central axes...
9030023 Bond pad stack for transistors  
A method for forming bond pads on a semiconductor die includes forming a dielectric stack including a bottom and top dielectric layer having a contact hole therethrough over a bond pad. An outer...
9030019 Semiconductor device and method of manufacture thereof  
A semiconductor device and a method of making a semiconductor device are disclosed. The semiconductor device comprises a redistribution layer arranged over a chip, the redistribution layer...
9030017 Z-connection using electroless plating  
An assembly includes a substrate having a substrate conductor and a contact at a first surface and a terminal at a second surface for electrically interconnecting the assembly with a component...
9029903 Light emitting diode package and method of manufacturing the same  
A light emitting diode package including a package body with a cavity, a plurality of light emitting diode (LED) chips in the cavity, a plurality of wires connected to the plurality of LED chips,...
9030014 Semiconductor device and method of manufacturing the same  
An upper surface of a plug (PL1) is formed so as to be higher than an upper surface of an interlayer insulating film (PIL) by forming the interlayer insulating film (PIL) on a semiconductor...
9024444 Semiconductor device  
In a semiconductor device, a first contact-diffusion-layer is in a first well to be connected to the first well and extends in a channel width direction of a first transistor in a first well. A...
9024447 Stackable electronic package and method of making same  
An apparatus comprises a first chip layer comprising a first component coupled to a first side of a first flex layer, the first component comprising a plurality of electrical pads. The first chip...
9024443 Semiconductor device and manufacturing method thereof  
A semiconductor device according to the present embodiment includes a semiconductor substrate. A lower-layer wiring is provided above a surface of the semiconductor substrate. An interlayer...
9018750 Thin film structure for high density inductors and redistribution in wafer level packaging  
Disclosed is a package that includes a wafer substrate and a metal stack seed layer. The metal stack seed layer includes a titanium thin film outer layer. A resist layer is provided in contact...
9018760 Solder interconnect with non-wettable sidewall pillars and methods of manufacture  
A solder interconnect structure is provided with non-wettable sidewalls and methods of manufacturing the same. The method includes forming a nickel or nickel alloy pillar on an underlying surface....
9018755 Joint structure and semiconductor device storage package  
A joint structure includes: a ceramic member; a metallized layer formed on a surface of the ceramic member; and a metal member joined to the metallized layer via a brazing material. The metal...
9018044 Chip-on-lead package and method of forming  
In one embodiment, a chip-on-lead package structures includes an electronic chip having opposing major surfaces. One major surface of the electronic chip is attached to first and second leads. The...
9013029 Joined body having an anti-corrosion film formed around a junction portion, and a semiconductor device having the same  
A joined body which is formed by, first, an aqueous solution containing an oxide film remover is disposed on a junction region of a first metal plate. Then, with the aqueous solution remaining on...
9013039 Wafer support system for 3D packaging  
A method for handling and supporting a device wafer during a wafer thinning process and the resulting device are provided. Embodiments include forming a plurality of solder bumps on a first...
9013040 Memory device with die stacking and heat dissipation  
A memory device with die stacking is provided. A plurality of substrates layers are stacked together into a stack. Each substrate layer may include a substrate having a plurality of cavities to...
9013043 Semiconductor element applicable to optical products  
A semiconductor element includes: a transparent substrate; a stack structure formed on the transparent substrate and having a metal oxide layer partially exposed through sidewalls of the stack...
9013002 Iridium interfacial stack (IRIS)  
An iridium interfacial stack (“IrIS”) and a method for producing the same are provided. The IrIS may include ordered layers of TaSi2, platinum, iridium, and platinum, and may be placed on top of a...
9006890 Solder in cavity interconnection structures  
The present disclosure relates to the field of fabricating microelectronic packages, wherein cavities are formed in a dielectric layer deposited on a first substrate to maintain separation between...
9006098 Impedance controlled electrical interconnection employing meta-materials  
A method of improving electrical interconnections between two electrical elements is made available by providing a meta-material overlay in conjunction with the electrical interconnection. The...
9006901 Thin power device and preparation method thereof  
A thin power device comprises a substrate having a first set of first contact pads at a front surface of the substrate electrically connecting to a second set of second contact pads at a back...
9006872 Semiconductor chip package having via hole and semiconductor module thereof  
In one embodiment, a semiconductor chip package includes an insulation frame having an opening part formed in a center thereof and a via hole formed around the opening part; a semiconductor chip...
9006911 Method for forming patterns of dense conductor lines and their contact pads, and memory array having dense conductor lines and contact pads  
A method for forming patterns of dense conductor lines and their contact pads is described. Parallel base line patterns are formed over a substrate. Each of the base line patterns is trimmed....
9006902 Semiconductor devices having through silicon vias and methods of fabricating the same  
A semiconductor device is provided having an insulating layer on a semiconductor substrate. The insulating layer and the semiconductor substrate define a through hole penetrating the semiconductor...
9006884 Three dimensional semiconductor device including pads  
A semiconductor device includes a substrate in which a cell region and a contact region are defined, a pad structure including a plurality of first conductive layers and a plurality of first...
9000583 Multiple die in a face down package  
A microelectronic package includes a subassembly including a first substrate and first and second microelectronic elements having contact-bearing faces facing towards oppositely-facing first and...
8999765 Methods to prevent filler entrapment in microelectronic device to microelectronic substrate interconnection structures  
Embodiments of the present description include methods for attaching a microelectronic device to a microelectronic substrate with interconnection structures after disposing of an underfill...
9000563 Capacitor and register of semiconductor device, memory system including the semiconductor device, and method of manufacturing the semiconductor device  
A capacitor of a semiconductor device includes a capacitor structure configured to include electrode layers and dielectric layers alternately stacked, edge regions each stepwise patterned, and a...
9000598 Orientation-independent device configuration and assembly  
The present disclosure is directed to orientation-independent device configuration and assembly. An electronic device may comprise conductive pads arranged concentrically on a surface of the...
9000587 Wafer-level thin chip integration  
A wafer-level package device and techniques for fabricating the device are described that include embedding a silicon chip onto an active device wafer or a passive device wafer, where the embedded...
9000597 Dummy structures and methods  
A semiconductor device and a method of making a semiconductor device are disclosed. The method of manufacturing a semiconductor device comprises forming a material layer on a substrate, patterning...
8999759 Method for fabricating packaging structure having embedded semiconductor element  
A method for fabricating a packaging structure having an embedded semiconductor element includes: providing a substrate having opposite first and second surfaces and at least an opening...
8993381 Method for forming a thin semiconductor device  
A method for forming a thin semiconductor device is disclosed. In one embodiment, a lead frame is provided over a carrier. At least one semiconductor chip is provided on the lead frame and the at...
8994187 Semiconductor device, circuit substrate, and electronic device  
A semiconductor device has a through electrode formed in a through hole which penetrates a Si substrate from one surface to the other surface of the Si substrate, wherein a rectangular electrode...
8994161 Semiconductor device package and methods for producing same  
Some embodiments have a semiconductor chip supported above a substrate, a filler layer encapsulating the semiconductor chip, a heat sink; and through contacts extending upwardly from the substrate...
8994133 Multi-layer input/output pad ring for solid state device controller  
Some embodiments of the disclosed subject matter include an integrated circuit. The integrated circuit includes a solid state device controller configured to control a plurality of flash memory...
8994179 Semiconductor device and method for making same  
One or more embodiments relate to a semiconductor device that includes: a conductive layer including a sidewall; a conductive capping layer disposed over the conductive layer and laterally...