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8159068 Semiconductor device  
A semiconductor device includes: a semiconductor layer composed of one of GaAs based semiconductor, InP-based semiconductor, and GaN-based semiconductor; a first silicon nitride film that is...
8154130 Self-aligned metal to form contacts to Ge containing substrates and structure formed thereby  
A method for forming germano-silicide contacts atop a Ge-containing layer that is more resistant to etching than are conventional silicide contacts that are formed from a pure metal is provided....
8129844 Method of forming a metal silicide layer, devices incorporating metal silicide layers and design structures for the devices  
Electronic devices and design structures of electronic devices containing metal silicide layers. The devices include: a thin silicide layer between two dielectric layers, at least one metal wire...
8115264 Semiconductor device having a metal gate with a low sheet resistance and method of fabricating metal gate of the same  
Provided is a semiconductor device that comprises a metal gate having a low sheet resistance characteristic and a high diffusion barrier characteristic and a method of fabricating the metal gate of...
8114720 Semiconductor device and manufacturing method thereof  
An object is to reduce a capacitance value of parasitic capacitance without decreasing driving capability of a transistor in a semiconductor device such as an active matrix display device. Further,...
8101871 Aluminum bond pads with enhanced wire bond stability  
An electronic device bond pad includes an Al layer located over an electronic device substrate. The Al layer includes an intrinsic group 10 metal located therein.
8076781 Semiconductor device and manufacturing method of the same  
A conventional semiconductor device has a problem that reduction of a connection resistance value between wiring layers is difficult because of an oxide film formed between the wiring layers. In a...
8072076 Bond pad structures and integrated circuit chip having the same  
Bonding pad structures and integrated circuits having the same are provided. An exemplary embodiment of a bond pad structure comprises a bond pad layer. A passivation layer partially covers the...
8044514 Semiconductor integrated circuit  
In a semiconductor integrated circuit, a second wiring layer includes a ground conductor having at least one opening formed therein. At least one opening is overlapped by at least one patch...
8030777 Protection of Cu damascene interconnects by formation of a self-aligned buffer layer  
Methods of protecting exposed metal damascene interconnect surfaces in a process for making electronic components and the electronic components made according to such methods. An integrated circuit...
8022482 Device configuration of asymmetrical DMOSFET with schottky barrier source  
A trenched semiconductor power device includes a trenched gate insulated by a gate insulation layer and surrounded by a source region encompassed in a body region above a drain region disposed on a...
8013446 Nitrogen-containing metal cap for interconnect structures  
An interconnect structure is provided that has enhanced electromigration reliability without degrading circuit short yield, and improved technology extendibility. The inventive interconnect...
7998858 Vertical interconnect structure, memory device and associated production method  
The present invention relates to a method for producing a vertical interconnect structure, a memory device and an associated production method, in which case, after the formation of a contact...
7985668 Method for forming a metal silicide having a lower potential for containing material defects  
Generally, the present disclosure is directed to a method of removing “weakened” areas of a metal silicide layer during silicide layer formation, thereby reducing the likelihood that material def...
7960832 Integrated circuit arrangement with layer stack  
An integrated circuit arrangement includes an electrically conductive conduction structure made from copper or a copper alloy. At a side wall of the conduction structure, there is a layer stack...
7955908 Thin film transistor array panel and manufacturing method thereof  
A thin film transistor array panel is provided, which includes: a gate line, a gate insulating layer, and a semiconductor layer sequentially formed on a substrate; a data line and a drain electrode...
7928571 Device having dual etch stop liner and reformed silicide layer and related methods  
The present invention provides a semiconductor device having dual silicon nitride liners and a reformed silicide layer and related methods for the manufacture of such a device. The reformed...
7915735 Selective metal deposition over dielectric layers  
Selective deposition of metal over dielectric layers in a manner that minimizes or eliminates keyhole formation is provided. According to one embodiment, a dielectric target layer is formed over a...
7851916 Strain silicon wafer with a crystal orientation (100) in flip chip BGA package  
A method and system is disclosed for better packaging semiconductor devices. In one example, a semiconductor device package comprises a package substrate, at least one die with an orientation of...
7847410 Interconnect of group III-V semiconductor device and fabrication method for making the same  
An interconnect of the group III-V semiconductor device and the fabrication method for making the same are described. The interconnect includes a first adhesion layer, a diffusion barrier layer for...
7830010 Surface treatment for selective metal cap applications  
Interconnect structures in which a noble metal-containing cap layer is present directly on a non-recessed surface of a conductive material which is embedded within a low k dielectric material are...
7825516 Formation of aligned capped metal lines and interconnections in multilevel semiconductor structures  
In integrated circuit technology; an electromigration and diffusion sensitive conductor of a metal such as copper and processing procedure therefore is provided, wherein, at a planarized chemical...
7807571 Semiconductor device and methods of forming the same  
An example embodiment provides a method of forming a conductive pattern in a semiconductor device. The method includes forming one or more dielectric layers over a first conductive pattern formed...
7807538 Method of forming a silicide layer while applying a compressive or tensile strain to impurity layers  
A metal insulator semiconductor field effect transistor (MISFET) having a strained channel region is disclosed. Also disclosed is a method of fabricating a semiconductor device having a...
7799682 Transistor having a locally provided metal silicide region in contact areas and a method of forming the transistor  
By performing a silicidation process on the basis of a patterned dielectric layer, such as an interlayer dielectric material, the respective metal silicide portions may be provided in a highly...
7786837 Semiconductor power device having a stacked discrete inductor structure  
A power device includes a discrete inductor having contacts formed on a first surface of the discrete inductor and at least one semiconductor component mounted on the first surface of the discrete...
7777344 Transitional interface between metal and dielectric in interconnect structures  
An integrated circuit structure and methods for forming the same are provided. The integrated circuit structure includes a semiconductor substrate; a dielectric layer over the semiconductor...
7750471 Metal and alloy silicides on a single silicon wafer  
Methods and apparatus relating to a single silicon wafer having metal and alloy silicides are described. In one embodiment, two different silicides may be provided on the same wafer. Other...
7732331 Copper interconnect structure having stuffed diffusion barrier  
The present invention provides a method of fabricating a semiconductor device, which could advance the commercialization of semiconductor devices with a copper interconnect. In a process of metal...
7719044 Platinum-containing integrated circuits and capacitor constructions  
In one aspect, the invention includes a method of forming a roughened layer of platinum, comprising: a) providing a substrate within a reaction chamber; b) flowing an oxidizing gas into the...
7655567 Methods for improving uniformity and resistivity of thin tungsten films  
The methods described herein relate to deposition of low resistivity, highly conformal tungsten nucleation layers. These layers serve as a seed layers for the deposition of a tungsten bulk layer....
7649263 Semiconductor device  
A semiconductor device including at least one conductive structure is provided. The conductive structure includes a silicon-containing conductive layer, a refractory metal salicide layer and a...
7638800 Wire for a display device, a method for manufacturing the same, a thin film transistor array panel including the wire, and a method for manufacturing the same  
First, a Cr film and a CrOx film are deposited and patterned using an etchant including 8-12% Ce(NH4)2(NO3)6, 10-20% NH3 and remaining ultra pure water to form a gate wire including a plurality of...
7615868 Electrode, method for producing same and semiconductor device using same  
There is provided a technology for obtaining an electrode having a low contact resistance and less surface roughness. There is provided an electrode comprising a semiconductor film 101, and a first...
7586196 Apparatus for an improved air gap interconnect structure  
In one embodiment, an apparatus comprises a first layer having at least one interconnect formed in an interlayer dielectric (ILD), a second layer formed over the first layer having a second at...
7541284 Method of depositing Ru films having high density  
A ruthenium film deposition method is disclosed. In one embodiment of the method, a first ruthenium film is deposited by using a PEALD process until a substrate is substantially entirely covered...
7494607 Electroconductive thick film composition(s), electrode(s), and semiconductor device(s) formed therefrom  
The present invention is directed to an electroconductive thick film composition comprising: (a) electroconductive metal particles selected from (1) Al, Cu, Au, Ag, Pd and Pt; (2) alloy of Al, Cu,...
7479687 Deep via seed repair using electroless plating chemistry  
Methods of forming a continuous seed layer in a high aspect via and its associated structures are described. Those methods comprise forming a recess in a substrate, forming a non-continuous metal...
7479682 Structure of a field effect transistor having metallic silicide and manufacturing method thereof  
A field effect transistor having metallic silicide layers is formed in a semiconductor layer on an insulating layer of an SOI substrate. The metallic silicide layers are composed of refractory...
7432202 Method of substrate manufacture that decreases the package resistance  
A method includes forming a coating on a land contact of a package substrate, the coating including a first material disposed between a first layer and a second layer, each of the first layer and...
7422707 Highly conductive composition for wafer coating  
A conductive composition for coating a semiconductor wafer comprises conductive filler that has an average particle size of less than 2 microns and a maximum particle size of less than 10 microns,...
7420227 Cu-metalized compound semiconductor device  
The present invention is a compound semiconductor device characterized in that it is Cu-metalized to improved the reliability of the device and to greatly reduce the cost of production.
7414291 Semiconductor device and method of manufacturing the same  
A method includes the steps of: implanting boron into a surface region of a silicon substrate to form a p+ diffused region; implanting indium into the surface of the p+ diffused region, to form an...
7399702 Methods of forming silicide  
Methods of fully siliciding semiconductive materials of semiconductor devices are disclosed. A preferred embodiment comprises depositing an alloy comprised of a first metal and a second metal over...
7385287 Preventing damage to low-k materials during resist stripping  
A method of forming a feature in a low-k dielectric layer is provided. A low-k dielectric layer is placed over a substrate. A patterned photoresist mask is placed over the low-k dielectric layer....
7368823 Semiconductor device and method of manufacturing the same  
A method of manufacturing a semiconductor device having an interconnection part formed of multiple carbon nanotubes is disclosed. The method includes the steps of (a) forming a growth mode control...
7348265 Semiconductor device having a silicided gate electrode and method of manufacture therefor  
The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the semiconductor device. The semiconductor device (100), among other...
7332435 Silicide structure for ultra-shallow junction for MOS devices  
A method of forming a semiconductor device comprising: forming a gate dielectric layer over a channel region; forming a gate electrode on the gate dielectric layer; forming source/drain regions...
7303988 Methods of manufacturing multi-level metal lines in semiconductor devices  
Methods of forming a multi-level metal line of a semiconductor device are disclosed. One example method includes subsequently stacking first and second metal layers, wherein a conductive etching...
7291920 Semiconductor structures  
In one aspect, the invention includes a method of forming a roughened layer of platinum, comprising: a) providing a substrate within a reaction chamber; b) flowing an oxidizing gas into the...
Matches 1 - 50 out of 346 1 2 3 4 5 6 7 >