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7598614 Low leakage metal-containing cap process using oxidation  
An interconnect structure which includes a metal-containing cap located atop each conductive feature that is present within a dielectric material is provided in which a surface region of the...
7586198 Innerlayer panels and printed wiring boards with embedded fiducials  
Innerlayer panels are provided with high density fiducials during manufacture. The fiducials can be identified using X-rays without etching away portions of the innerlayer panel to expose the...
7547972 Laminated structure, very-large-scale integrated circuit wiring board, and method of formation thereof  
The laminated structure includes a substrate of low dielectric constant material of silicon compound and an electroless copper plating layer laminated thereon with a barrier layer. The barrier...
7533193 Apparatus and method for reducing electromigration  
An apparatus and method therefor wherein instead of applying a high bias voltage 100 per cent of the time to leads susceptible to dendrite formation, the bias voltage is switched from a low bias...
7511378 Enhancement of performance of a conductive wire in a multilayered substrate  
An electronic structure having wiring, and an associated method of designing the structure, for limiting a temperature gradient in the wiring. The electronic structure includes a substrate having a...
7508082 Semiconductor device and method of manufacturing the same  
There is provided a solution to the problem of the poor adhesion in the pad portion while inhibiting the dishing in the pad portion. An SiON film, which covers insulating areas and has an opening...
7504674 Electronic apparatus having a core conductive structure within an insulating layer  
Electronic devices are constructed by a method that includes forming a first conductive layer in an opening in a multilayer dielectric structure supported by a substrate, forming a core conductive...
7495338 Metal capped copper interconnect  
A conducting material comprising: a conducting core region comprising copper and from 0.001 atomic percent to 0.6 atomic percent of one or more metals selected from iridium, osmium and rhenium; and...
7495317 Semiconductor package with ferrite shielding structure  
A semiconductor device comprises at the wafer level one or more ferrite structures adapted to dampen high frequency noise potentially apparent at signal lines and termination points within the...
7446392 Electronic device and method for manufacturing the same  
An electronic device is provided using wiring comprising aluminum to prevent hillock or whisker from generating, wherein the wiring contains oxygen atoms at a concentration of 8×10 18 atoms·cm...
7436066 Semiconductor element  
It is an object of the present invention to provide a highly reliable and high-quality semiconductor element by effectively preventing the migration of silver to a nitride semiconductor when an...
7422977 Copper adhesion improvement device and method  
A semiconductor device, in which a semiconductor integrated circuit having a multi-level interconnection structure is formed, according to an embodiment of the present invention, comprises a copper...
7414275 Multi-level interconnections for an integrated circuit chip  
Multilevel metallization layouts for an integrated circuit chip including transistors having first, second and third elements to which metallization layouts connect. The layouts minimize current...
7372160 Barrier film deposition over metal for reduction in metal dishing after CMP  
A protective barrier layer, formed of a material such as titanium or titanium nitride for which removal by chemical mechanical polishing (CMP) is primarily mechanical rather than primarily...
7339274 Metallization performance in electronic devices  
Phenomena such as electromigration and stress-induced migration occurring in metal interconnects of devices such as integrated circuits are inhibited by use of underlying non-planarities. Thus the...
7303988 Methods of manufacturing multi-level metal lines in semiconductor devices  
Methods of forming a multi-level metal line of a semiconductor device are disclosed. One example method includes subsequently stacking first and second metal layers, wherein a conductive etching...
7301239 Wiring structure to minimize stress induced void formation  
A wiring structure with improved resistance to void formation and a method of making the same are described. The wiring structure has a first conducting layer that includes a large area portion...
7276796 Formation of oxidation-resistant seed layer for interconnect applications  
An interconnect structure of the single or dual damascene type and a method of forming the same, which substantially reduces the surface oxidation problem of plating a conductive material onto a...
7271097 Method for manufacturing a semiconductor protection element and a semiconductor device  
A semiconductor protection element is provided in which no heat generation occurs in a concentrated manner, in a region having a high resistance value even when electrostatic discharge (ESD) is...
7271700 Thin film resistor with current density enhancing layer (CDEL)  
A thin film resistor device and method of manufacture includes a layer of a thin film conductor material and a current density enhancing layer (CDEL). The CDEL is an insulator material adapted to...
7262473 Metal to polysilicon contact in oxygen environment  
A method for forming a contact capable of tolerating an O 2 environment up to several hundred degrees Celsius for several hours is disclosed. To slow down the metal oxide front of the metal layer...
7242097 Electromigration barrier layers for solder joints  
A microelectronic package is disclosed including a microelectronic device, a substrate, and a signaling path coupling the microelectronic device with the substrate. The signaling path includes a...
7238626 Chemically and electrically stabilized polymer films  
A method of stabilizing a poly(paraxylylene) dielectric thin film after forming the dielectric thin film via transport polymerization is disclosed, wherein the method includes annealing the...
7233071 Low-k dielectric layer based upon carbon nanostructures  
A low-k dielectric material for use in the manufacture of semiconductor devices, semiconductor structures using the low-k dielectric material, and methods of forming such dielectric materials and...
7224009 Method for forming a low leakage contact in a CMOS imager  
An imaging device formed as a CMOS semiconductor integrated circuit includes a doped polysilicon contact line between the floating diffusion region and the gate of a source follower output...
7224063 Dual-damascene metallization interconnection  
An interconnect structure, comprising: a lower level wire having a side and a bottom, the lower level wire comprising: a lower core conductor and a lower conductive liner, the lower conductive...
7215029 Multilayer interconnection structure of a semiconductor  
In order to solve the aforementioned problems, the present-invention provides a semiconductor device having a multilayer interconnection structure, wherein an upper interconnection comprises a...
7205667 Semiconductor device having copper wiring  
A first interlayer insulating film made of insulting material is formed over an underlying substrate. A via hole is formed through the first interlayer insulating film. A conductive plug made of...
7196420 Method and structure for creating ultra low resistance damascene copper wiring  
A low resistance copper damascene interconnect structure is formed by providing a thin dielectric film such as SiC or SiOC formed on the sidewalls of the via and trench structures to function as a...
7193327 Barrier structure for semiconductor devices  
An opening in a dielectric layer having a unique barrier layer structure is provided. In an embodiment, the opening is a via and a trench. The barrier layer, which may comprise one or more barrier...
7187079 Stacked memory cell having diffusion barriers  
A nonconductive hydrogen barrier layer is deposited on a substrate and completely covers the surface area over a memory capacitor and a MOSFET switch of an integrated circuit memory cell. A portion...
7187080 Semiconductor device with a conductive layer including a copper layer with a dopant  
A method of manufacturing a semiconductor device includes the steps of providing a semiconductor substrate ( 202 ), forming a dielectric layer ( 204 ) over the semiconductor substrate ( 202 ), and...
7164206 Structure in a microelectronic device including a bi-layer for a diffusion barrier and an etch-stop layer  
The invention relates to a microelectronic device and a structure therein that includes a diffusion barrier layer having a first thickness and a first dielectric constant. An etch stop layer is...
7164207 Wiring structure for semiconductor device  
A wiring structure for semiconductor device has a wiring layer that includes copper as main component and a crystal grain promotion layer that promotes enlargement in a crystal grain of the wiring...
7164205 Semiconductor carrier film, and semiconductor device and liquid crystal module using the same  
A semiconductor carrier film includes (i) a base film having insulating property, (ii) a barrier layer provided on the base film, the barrier layer including nickel-chrome alloy as a main...
7151315 Method of a non-metal barrier copper damascene integration  
The present disclosure provides a method, integrated circuit, and interconnect structure utilizing non-metal barrier copper damascene integration. The method is provided for fabricating an...
7145241 Semiconductor device having a multilayer interconnection structure and fabrication process thereof  
A multilayer interconnection structure includes a first interconnection layer having a copper interconnection pattern and a second interconnection layer having an aluminum interconnection layer and...
7141880 Metal line stacking structure in semiconductor device and formation method thereof  
The method for forming a metal line stacking structure according to a preferred embodiment of the present invention comprises: sequentially forming a first barrier metal and a first metal layer on...
7129582 Reducing the migration of grain boundaries  
A method of forming a semiconductor device includes implanting a precipitate into a gate conductor of an at least partially formed semiconductor device. The gate conductor including a plurality of...
7115997 Seedless wirebond pad plating  
An integrated circuit (IC) chip, semiconductor wafer with IC chips in a number of die locations and a method of making the IC chips on the wafer. The IC chips have plated chip interconnect pads....
7088000 Method and structure to wire electronic devices  
An integrated circuit structure and a method of manufacturing, wherein the method comprises forming a first via in an interconnect layer of the substrate, wherein the first via comprises a first...
7087999 Semiconductor protection element, semiconductor device and method for manufacturing same  
A semiconductor protection element is provided in which no heat generation occurs in a concentrated manner, in a region having a high resistance value even when electrostatic discharge (ESD) is...
7081676 Structure for controlling the interface roughness of cobalt disilicide  
A method of producing electrical contacts having reduced interface roughness as well as the electrical contacts themselves are disclosed herein. The method of the present invention comprises (a)...
7042099 Semiconductor device containing a dummy wire  
There is disclosed a semiconductor device comprising a substrate, a first insulating film which is provided above the substrate and has a relative dielectric constant which is at most a...
7034398 Semiconductor device having contact plug and buried conductive film therein  
A semiconductor device includes an active element structure that is formed on a semiconductor substrate and has a connection region formed in the surface of the semiconductor substrate. A contact...
7030493 Semiconductor device having layered interconnect structure with a copper or platinum conducting film and a neighboring film  
Provided is a reliable semiconductor device with a layered interconnect structure that may develop no trouble of voids and interconnect breakdowns, in which the layered interconnect structure...
7030492 Under bump metallurgic layer  
An under bump metallurgic (UBM) layer which is adapted for a chip is disclosed. The UMM layer alleviate the loss of electromigration resulting from current crowing effect at the corner of UBM layer...
6992389 Barrier for interconnect and method  
A method of creating a multi-layered barrier for use in an interconnect, a barrier for an interconnect, and an interconnect including the barrier are disclosed. The method includes creating the...
6955980 Reducing the migration of grain boundaries  
A method of forming a semiconductor device includes implanting a precipitate into a gate conductor of an at least partially formed semiconductor device. The gate conductor including a plurality of...
6943435 Lead pin with Au-Ge based brazing material  
A lead pin with an Au—Ge based brazing material including a lead pin made of a copper-containing metal is provided. The lead pin including a joining surface to a substrate, at least the joining...
Matches 1 - 50 out of 341 1 2 3 4 5 6 7 >