Patents in Class 257/762

Matches 1 - 50 out of 839

Match	Document	Document Title
1	7605472	Interconnections having double capping layer and method for forming the same Provided are an interconnection of a semiconductor device which includes a capping layer and a method for forming the interconnection. The interconnection of the semiconductor device is a copper...
2	7605471	Semiconductor devices and methods for manufacturing the same Semiconductor devices having a copper line layer and methods for manufacturing the same are disclosed. An illustrated semiconductor device comprises a damascene insulating layer having a contact...
3	7605468	Barrier-metal-free copper damascene technology using atomic hydrogen enhanced reflow A method for forming conductive contacts and interconnects in a semiconductor structure, and the resulting conductive components are provided. In particular, the method is used to fabricate single...
4	7605460	Method and apparatus for a power distribution system A method and apparatus is provided to reduce the spreading inductance and increase the distributed capacitance of power planes within the power distribution system of a semiconductor package...
5	7595556	Semiconductor device and method for manufacturing the same Embodiments relate to a semiconductor device and a method for manufacturing the same. According to embodiments, the semiconductor device may include a semiconductor substrate formed with a metal...
6	7595553	Packaging board and manufacturing method therefor, semiconductor module and mobile apparatus An advantage of the present invention is to suppress moisture infiltrating from a pad electrode portion from spreading over the surface of a wiring pattern and improve the reliability of a...
7	7586197	Wire structure, method of forming wire, thin film transistor substrate, and method of manufacturing thin film transistor substrate Provided are a wire structure, a method of forming a wire, a thin film transistor (TFT) substrate, and a method of manufacturing the TFT substrate. The wire structure includes a barrier layer...
8	7579696	Semiconductor device A semiconductor device includes an effective wire formed above a substrate in a multilayer interconnection structure and having a first electrode pad in a top layer; a first reinforcing material...
9	7572728	Semiconductor device and method for manufacturing the same A semiconductor device and method with a dual damascene pattern uses buffer layers to prevent photoresist layer poisoning due to a reaction between an interlayer dielectric and a photoresist layer....
10	7569937	Technique for forming a copper-based contact layer without a terminal metal By directly forming an underbump metallization layer on a copper-based contact region, the formation of any other terminal metals, such as aluminum and corresponding adhesion/barrier layers may be...
11	7569476	Semiconductor integrated circuit device and a method of manufacturing the same In manufacturing a semiconductor integrated circuit device, an interconnect trench and a contact hole are formed in an interlayer insulating film formed over a first-level interconnect on a...
12	7566975	Semiconductor device and method for manufacturing the same A semiconductor device includes a semiconductor substrate, a copper-containing metal interconnect over the semiconductor substrate, and a copper-containing connection plug, and the metal...
13	7566973	Semiconductor device and method of manufacturing the same The method of manufacturing a semiconductor device according to the present invention includes: forming an interconnect trench in an insulating film formed on a semiconductor substrate (S 100 );...
14	7560814	Semiconductor device that improves electrical connection reliability A semiconductor device including: a semiconductor section in which an element is formed; an insulating layer formed on the semiconductor section; an electrode pad formed on the insulating layer; a...
15	7554202	Semiconductor integrated circuit device Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a...
16	7554199	Substrate for evaluation The CMP technology is provided for a damascene wiring structure having a plural-layer wiring that is excellent in flatness and resolvability of Cu residue. An evaluation substrate is provided for...
17	7553757	Semiconductor device and method of manufacturing the same An interlayer insulator includes a first interlayer insulator and a second interlayer insulator formed on the first interlayer insulator and having a property of preventing diffusion of copper. A...
18	7550822	Dual-damascene metal wiring patterns for integrated circuit devices Methods of forming dual-damascene metal wiring patterns include forming a first metal wiring pattern (e.g., copper wiring pattern) on an integrated circuit substrate and forming an etch-stop layer...
19	7547972	Laminated structure, very-large-scale integrated circuit wiring board, and method of formation thereof The laminated structure includes a substrate of low dielectric constant material of silicon compound and an electroless copper plating layer laminated thereon with a barrier layer. The barrier...
20	7535095	Printed wiring board and method for producing the same The present invention has for its object to provide a multilayer printed circuit board which is very satisfactory in fracture toughness, dielectric constant, adhesion and processability, among...
21	7525196	Protection of seedlayer for electroplating The present invention includes a method of providing a substrate; sequentially forming a seed layer over the substrate and forming a protection layer over the seed layer; and sequentially removing...
22	7521802	Semiconductor device having a refractory metal containing film and method for manufacturing the same A semiconductor device and a method for manufacturing the same of the present invention in which the semiconductor device is provided with a fuse structure or an electrode pad structure, suppress...
23	7508076	Information handling system including a circuitized substrate having a dielectric layer without continuous fibers An information handling system which includes as part thereof a circuitized substrate comprising a first layer comprised of a dielectric material including a resin material including a...
24	7504727	Semiconductor interconnect structure utilizing a porous dielectric material as an etch stop layer between adjacent non-porous dielectric materials Interconnect structures possessing a non-porous (dense) low-k organosilicate glass (OSG) film utilizing a porous low-k OSG film as an etch stop layer or a porous low-k OSG film using a non-porous...
25	7504724	Semiconductor device A semiconductor device comprises: a plurality of first wiring lines formed in a first layer with a first wiring width and a first wiring space; a plurality of second wiring lines formed in a second...
26	7504712	Electronic device with selective nickel palladium gold plated leadframe and method of making the same An electronic device comprises a leadframe attached to a die and embedded in a mold packaging with enhanced adhesion property. The leadframe comprises a bonding surface, a soldering surface, a mold...
27	7504674	Electronic apparatus having a core conductive structure within an insulating layer Electronic devices are constructed by a method that includes forming a first conductive layer in an opening in a multilayer dielectric structure supported by a substrate, forming a core conductive...
28	7498242	Plasma pre-treating surfaces for atomic layer deposition Method and structures are provided for conformal lining of dual damascene structures in integrated circuits. Preferred embodiments are directed to providing conformal lining over openings formed in...
29	7495338	Metal capped copper interconnect A conducting material comprising: a conducting core region comprising copper and from 0.001 atomic percent to 0.6 atomic percent of one or more metals selected from iridium, osmium and rhenium; and...
30	7495335	Method of reducing process steps in metal line protective structure formation A method of forming a protective structure on a top metal line on an interconnect structure is disclosed. The method includes providing a plate opening in the passivation layer on the top metal...
31	7482693	Top layers of metal for high performance IC's A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a...
32	7479700	Semiconductor device featuring copper wiring layers of different widths having metal capping layers of different thickness formed thereon, and method for manufacturing the same In a semiconductor device, an insulating interlayer is provided above a semiconductor substrate, and a plurality of first wiring layers and a plurality of second wiring layers are formed in the...
33	7479687	Deep via seed repair using electroless plating chemistry Methods of forming a continuous seed layer in a high aspect via and its associated structures are described. Those methods comprise forming a recess in a substrate, forming a non-continuous metal...
34	7476979	Chip scale surface mounted device and process of manufacture A chip scale package has a semiconductor MOSFET die which has a top electrode surface covered with a layer of a photosensitive liquid epoxy which is photolithographically patterned to expose...
35	7476971	Via line barrier and etch stop structure A semiconductor device and a method for making the semiconductor device having a barrier layer in a via hole region and a barrier layer in a via line region. The barrier layer in the via line...
36	7476564	Flip-chip packaging process using copper pillar as bump structure A flip-chip packaging process is disclosed. The present invention is featured in forming a copper pillar on a wafer, forming a solder on a substrate; and enabling the solder to substantially cover...
37	7473642	Method for fabricating conductive layer A method for fabricating a conductive layer is provided. First, a substrate is provided and a patterned adhesion layer is formed on the substrate. Next, a chemical plating process is performed to...
38	7470990	Low moisture absorptive circuitized substrate with reduced thermal expansion, method of making same, electrical assembly utilizing same, and information handling system utilizing same A circuitized substrate including a composite layer including a first dielectric sub-layer including a plurality of fibers having a low coefficient of thermal expansion and a second dielectric...
39	7462565	Method of manufacturing semiconductor device A substrate having a copper wiring is prepared. An insulating film is formed on the copper wiring. The insulating film is etched with a gas containing fluorine to form an opening reaching the...
40	7459787	Multi-layered copper line structure of semiconductor device and method for forming the same A multi-layered copper line structure of a semiconductor device with a lower copper line, an upper copper line, and a via contact, which electrically connects the lower copper line and the upper...
41	7456501	Semiconductor structure having recess with conductive metal A semiconductor structure includes a semiconductor substrate, a recess located in at least one major surface of the substrate, an electrical insulating layer located over the at least one major...
42	7449781	Printed wiring board A printed wiring board including solder pads excellent in frequency characteristic is provided. To do so, each solder pad 73 is formed by providing a single tin layer 74 on a conductor circuit 158...
43	7449780	Apparatus to minimize thermal impedance using copper on die backside A method and apparatus to minimize thermal impedance using copper on the die or chip backside. Some embodiments use deposited copper having a thickness chosen to complement a given chip thickness,...
44	7446393	Co-sputter deposition of metal-doped chalcogenides The present invention is related to methods and apparatus that allow a chalcogenide glass such as germanium selenide (Ge x Se 1-x ) to be doped with a metal such as silver, copper, or zinc without...
45	7443029	Adhesion of copper and etch stop layer for copper alloy A new method and structure is provided for the creation of a copper dual damascene interconnect. A dual damascene structure is created in the layer of dielectric, optionally a metal barrier layer...
46	7439624	Enhanced mechanical strength via contacts The present invention provides an enhanced interconnect structure with improved reliability. The inventive interconnect structure has enhanced mechanical strength of via contacts provided by...
47	7439182	Semiconductor device and method of fabricating the same A semiconductor and a method of fabricating the same are provided. The method includes: forming an insulation layer on a substrate; forming a trench by selectively etching the insulation layer;...
48	7436066	Semiconductor element It is an object of the present invention to provide a highly reliable and high-quality semiconductor element by effectively preventing the migration of silver to a nitride semiconductor when an...
49	7427563	Dielectric barrier films for use as copper barrier layers in semiconductor trench and via structures The present invention is directed to improved dielectric copper barrier layer and related interconnect structures. One structure includes a semiconductor substrate having a copper line. An...
50	7423347	In-situ deposition for cu hillock suppression A semiconductor interconnect structure having reduced hillock formation and a method for forming the same are provided. The semiconductor interconnect structure includes a conductor formed in a...

Matches 1 - 50 out of 839

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