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Match Document Document Title
7612453 Semiconductor device having an interconnect structure and a reinforcing insulating film  
A semiconductor device includes in an interconnect structure which includes a first interconnect made of a copper-containing metal, a first Cu silicide layer covering the upper portion of the first...
7605471 Semiconductor devices and methods for manufacturing the same  
Semiconductor devices having a copper line layer and methods for manufacturing the same are disclosed. An illustrated semiconductor device comprises a damascene insulating layer having a contact...
7602062 Package substrate with dual material build-up layers  
Multi-layered, organic build-up semiconductor package substrates have build-up layers with layers of both fibrous organic dielectric material and non-fibrous organic dielectric material....
7602048 Semiconductor device and semiconductor wafer having a multi-layered insulation film  
The object of the present invention is to improve the interfacial adhesion between the film with low dielectric constant and protective film, without damaging the excellent dielectric, flatness and...
7592710 Bond pad structure for wire bonding  
A bond pad structure of an integrated circuit is provided. The bond pad structure includes a conductive bond pad, a first dielectric layer underlying the bond pad, and an M top plate located in...
7586132 Power FET with low on-resistance using merged metal layers  
In one embodiment, relatively thin but wide metal bus strips overlying a high power FET are formed to conduct current to the source and drain narrow metal strips. A passivation layer is formed over...
7582970 Carbon containing silicon oxide film having high ashing tolerance and adhesion  
A semiconductor device includes an interlayer insulating film formed on or over a semiconductor substrate. An opening is formed in the interlayer insulating film and reaches a lower layer metal...
RE40887 Semiconductor chip with redistribution metal layer  
A new method is provided for the creation of Input/Output connection points to a semiconductor device package. An extension is applied to the conventional I/O connect points of a semiconductor...
7579272 Methods of forming low-k dielectric layers containing carbon nanostructures  
Methods of forming low-k dielectric layers for use in the manufacture of semiconductor devices and fabricating semiconductor structures using the low-k dielectric material. The low-k dielectric...
7566575 Mounting circuit and method for producing semiconductor-chip-mounting circuit  
A method according to the present invention for producing a semiconductor-chip-mounting circuit 1 includes mainly three steps. In a first step, contacts 2 each in the form of a conical helix...
7563707 Laser process for reliable and low-resistance electrical contacts  
Disclosed is a method for manufacturing an organic optoelectronic device. The method comprises providing a substrate, disposing a first electrode on the substrate, disposing a metal pad on the...
7554200 Semiconductor devices including porous insulators  
Semiconductor devices with porous insulative materials are disclosed. The porous insulative materials may include a consolidated material with voids dispersed therethrough. The voids may be defined...
7554168 Semiconductor acceleration sensor device  
A semiconductor device comprises a package having a cavity in the interior thereof, a chip having a semiconductor element, and an adhesive portion comprised of a silicone or fluorine resin and...
7550824 Low k interconnect dielectric using surface transformation  
Systems, devices and methods are provided to improve performance of integrated circuits by providing a low-k insulator. One aspect is an integrated circuit insulator structure. One embodiment...
7550788 Semiconductor device having fuse element arranged between electrodes formed in different wiring layers  
A semiconductor device includes a lower electrode, an upper electrode, and a fuse element that connects the lower electrode and the upper electrode. The height of the fuse element is greater than...
7547971 Semiconductor integrated circuit device  
Circuit elements and wirings constituting a circuit, and first electrodes electrically connected to such a circuit are provided on one main surface of a semiconductor substrate. An organic...
7544966 Three-terminal electrical bistable devices  
A three terminal electrical bistable device that includes a tri-layer composed of an electrically conductive mixed layer sandwiched between two layers of low conductivity organic material that is...
7541679 Exposed pore sealing post patterning  
Methods and structures having pore-closing layers for closing exposed pores in a patterned porous low-k dielectric layer, and optionally a reactive liner on the low-k dielectric. A first reactant...
7541646 Thin film transistor device and method of manufacturing the same  
A thin film transistor device according to an embodiment of the invention includes: a thin film transistor having a silicon layer including a source region, a drain region, and a channel region, a...
7538434 Copper interconnection with conductive polymer layer and method of forming the same  
A conductive polymer between two metallic layers acts a glue layer, a barrier layer or an activation seed layer. The conductive polymer layer is employed to encapsulate a copper interconnection...
7521802 Semiconductor device having a refractory metal containing film and method for manufacturing the same  
A semiconductor device and a method for manufacturing the same of the present invention in which the semiconductor device is provided with a fuse structure or an electrode pad structure, suppress...
7521381 Method for producing silicon wafer and silicon wafer  
A silicon wafer is thermal-annealed in an atmosphere to form new vacancies therein by thermal annealing and the atmosphere in the thermal annealing contains a nitride gas having a lower...
7518245 Contact structure of a semiconductor device  
In one embodiment, a semiconductor device comprises a conductive pad formed in a semiconductor substrate. The semiconductor device further includes a conductive pattern overlying a peripheral...
7518244 Reducing line to line capacitance using oriented dielectric films  
By exposing dielectrics to a strong electric field, anisotropic characteristics may be introduced into the dielectric. This may result in the dielectric having different dielectric constants in...
7514779 Multilayer build-up wiring board  
Mesh holes 35 a and 59 a of upper solid layers 35 and upper solid layers 59 are formed to overlie on one another, so that the insulating properties of interlayer resin insulating layers 50...
7511296 Organic semiconductor device, field-effect transistor, and their manufacturing methods  
An organic semiconductor device is provided which includes an organic semiconductor layer and an insulating layer. The insulating layer is made of a cured material formed from a composition...
7504727 Semiconductor interconnect structure utilizing a porous dielectric material as an etch stop layer between adjacent non-porous dielectric materials  
Interconnect structures possessing a non-porous (dense) low-k organosilicate glass (OSG) film utilizing a porous low-k OSG film as an etch stop layer or a porous low-k OSG film using a non-porous...
7504719 Printed wiring board having a roughened surface formed on a metal layer, and method for producing the same  
The present invention has for its object to provide a multilayer printed circuit board which is very satisfactory in facture toughness, dielectric constant, adhesion and processability, among other...
7504709 Electronic device, method of manufacturing an electronic device, and electronic apparatus  
An electronic device including: a pair of electrodes; an organic semiconductor layer; and an organic film formed of organic compounds including nonconjugated organic compounds coupled to at least...
7504699 Fabrication of a semiconductor device with air gaps for ultra-low capacitance interconnections  
A method of forming an air gap or gaps within solid structures and specifically semiconductor structures to reduce capacitive coupling between electrical elements such as metal lines, wherein a...
7489038 Design of BEOL patterns to reduce the stresses on structures below chip bondpads  
A semiconductor structure comprising a substrate including a first layer comprising a first material having a first modulus of elasticity; a first structure comprising a conductor and formed within...
7485964 Dielectric material  
A dielectric material formed by contacting a low dielectric constant polymer with liquid or supercritical carbon dioxide, under thermodynamic conditions which maintain the carbon dioxide in the...
7485915 Semiconductor device and method having capacitor and capacitor insulating film that includes preset metal element  
A semiconductor device includes a capacitor which includes a capacitor insulating film at least including a first insulating film and a ferroelectric film formed in contact with the first...
7485569 Printed circuit board including embedded chips and method of fabricating the same  
A printed circuit board having embedded chips, composed of a central layer having an embedded chip, an insulating layer formed on one surface or both surfaces of the central layer and having a via...
7479671 Thin film phase change memory cell formed on silicon-on-insulator substrate  
A memory cell includes a semiconductor feature and a phase change material. The semiconductor feature defines a groove that divides the semiconductor feature into a first electrode and a second...
7474002 Semiconductor device having dielectric film having aperture portion  
In the semiconductor device having a structure in which a plurality of layers are built-up by layers made of different materials or layers including various formed patterns, it is an object to...
7470988 Chip structure and process for forming the same  
A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate....
7466028 Semiconductor contact structure  
A semiconductor device structure for a three-dimensional integrated circuit is provided. The semiconductor device structure includes: a substrate having a first surface and a second surface; a via...
7465656 Semiconductor device and method for fabricating the same  
A semiconductor device includes a conductive pattern formed on a substrate, a conductive land formed to come into contact with at least part of the top surface of the conductive pattern, and a...
7459389 Method of forming a semiconductor device having air gaps and the structure so formed  
A method of forming a semiconductor device. Depositing alternating layers of a first and a second dielectric material, wherein the first and second dielectric materials are selectively etchable at...
7452802 Method of forming metal wiring for high voltage element  
Disclosed herein is a method of forming metal wirings for high voltage elements. According to the present invention, after a copper film is formed, a wet etch process using an interlayer insulating...
7449408 Method for manufacturing semiconductor device  
It is an object of the present invention to provide a method for manufacturing a semiconductor device in which a desired region can be etched by evenly applying a solution including a resist and a...
7446418 Semiconductor device for preventing defective filling of interconnection and cracking of insulating film  
The semiconductor device has insulating films 40, 42 formed over a substrate 10 ; an interconnection 58 buried in at least a surface side of the insulating films 40, 42 ; insulating films ...
7429793 Semiconductor device having an electronic circuit disposed therein  
A semiconductor device and a fabrication method thereof are provided. A semiconductor device which is packaged as it includes a semiconductor in which an electronic circuit is disposed, the...
7425735 Multi-layer phase-changeable memory devices  
A phase-changeable memory device includes a phase-changeable material pattern and first and second electrodes electrically connected to the phase-changeable material pattern. The first and second...
7423346 Post passivation interconnection process and structures  
A system and method for forming post passivation metal structures is described. Metal interconnections and high quality electrical components, such as inductors, transformers, capacitors, or...
7423300 Single-mask phase change memory element  
A memory device. An array of memory elements is formed on a semiconductor chip. A parallel array of word lines extends in a first direction, connecting each memory element to a data source, and a...
7422975 Composite inter-level dielectric structure for an integrated circuit  
A method is provided for making an inter-level dielectric for a microelectronic device formed on a substrate. The method begins by forming first and second spacer layers over a substrate layer. The...
7420279 Carbon containing silicon oxide film having high ashing tolerance and adhesion  
An insulating film used for an interlayer insulating film of a semiconductor device and having a low dielectric constant. The insulating film comprises a carbon containing silicon oxide (SiOCH)...
7420276 Post passivation structure for semiconductor chip or wafer  
The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor wafer, post-passivation. The thick,...
Matches 1 - 50 out of 513 1 2 3 4 5 6 7 8 9 10 11 >