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Match Document Document Title
8183581 LED arrangement  
An LED arrangement (light emitting diode) has a plurality of adjacent radiating LEDs that are nearly identically aligned for forming an extended area light source. The LEDs are attached to a...
8183663 Crack resistant circuit under pad structure and method of manufacturing the same  
A circuit under pad structure includes a substrate, a pad electrode, wiring layers interlayer insulation layers alternately disposed between the pad electrode and the substrate, and at least one...
8183698 Bond pad support structure for semiconductor device  
According to certain embodiments, integrated circuits are fabricated using brittle low-k dielectric material to reduce undesired capacitances between conductive structures. To avoid permanent...
8183691 Semiconductor device with pads overlapping wiring layers including dummy wiring  
A semiconductor device includes plural electrode pads arranged in an active region of a semiconductor chip, and wiring layers provided below the plural electrode pads wherein occupation rates of...
8183160 Method for manufacturing a semiconductor device and semiconductor device obtainable with such a method  
A method for manufacturing a semiconductor device includes providing a patterned hard-mask layer. The hard-mask layer is provided on an exposed surface of one or more layers to be patterned of a...
8183150 Semiconductor device having silicon carbide and conductive pathway interface  
The present invention provides semiconductor device formed by an in situ plasma reducing process to reduce oxides or other contaminants, using a compound of nitrogen and hydrogen, typically...
8183081 Hybrid heterojunction solar cell fabrication using a metal layer mask  
Embodiments of the invention generally provide a high efficiency solar cell using a novel processing sequence to form a solar cell device. In one embodiment, the methods include forming one or more...
8178964 Semiconductor device package with die receiving through-hole and dual build-up layers over both side-surfaces for WLP and method of the same  
A structure of a semiconductor device package having a substrate with a die receiving through hole, a connecting through hole structure and a contact pad. A die is disposed within the die receiving...
8178909 Integrated circuit cell architecture configurable for memory or logic elements  
An improved integrated circuit cell architecture is provided for configurability between a memory cell or logic elements. The cell architecture is configured on variable layers above a first layer...
8178981 Semiconductor device  
The present invention aims at offering the semiconductor device which can improve the strength to the stress generated with a bonding pad. In the semiconductor device concerning the present...
8178436 Adhesion and electromigration performance at an interface between a dielectric and metal  
Interconnect structures having improved adhesion and electromigration performance and methods to fabricate thereof are described. A tensile capping layer is formed on a first conductive layer on a...
8178908 Electrical contact structure having multiple metal interconnect levels staggering one another  
An electrical contact structure distributes current along a length thereof. The electrical contact structure includes a plurality of n metal rectangles on n levels of metal. The rectangle on one...
8174098 Semiconductor device and method of providing a thermal dissipation path through RDL and conductive via  
A semiconductor device has a conductive via formed around a perimeter of the semiconductor die. First and second conductive layers are formed on opposite sides of the semiconductor die and...
8174011 Positional offset measurement pattern unit featuring via-plug and interconnections, and method using such positional offset measurement pattern unit  
In a positional offset measurement pattern unit formed in an insulating layer, a first interconnection is formed in the insulating layer. A via-plug is formed in the insulating layer so as to be...
8174093 Multichip semiconductor device, chip therefor and method of formation thereof  
A multichip semiconductor device is disclosed in which chips are stacked each of which comprises a semiconductor substrate formed on top with circuit components and an interlayer insulating film...
8169081 Conductive routings in integrated circuits using under bump metallization  
An integrated circuit structure includes a first conductive layer and an under bump metallization layer over the first conductive layer. The first conductive layer has a first conductive region and...
8168530 Methods of forming one transistor DRAM devices  
A one transistor DRAM device includes: a substrate with an insulating layer, a first semiconductor layer provided on the insulating layer and including a first source region and a first region...
8169071 Semiconductor device having vertically offset bond on trace interconnects on recessed and raised bond fingers  
A semiconductor device includes a substrate, a first recessed conductive layer embedded and recessed into a first surface of the substrate, and a first raised conductive layer disposed above the...
8168471 Semiconductor device and manufacturing method of a semiconductor device  
A semiconductor device includes a multi-layer substrate and a semiconductor element mounted on the multi-layer substrate. The multi-layer substrate contains a plurality of circuit-formation layers...
8169084 Bond pad structure and method for producing same  
It is described a bond pad structure and a method for producing the same, the bond pad structure (1), comprising: a substrate (3) having a surface (17) to be electrically contacted; a first...
8169080 Semiconductor device and method of manufacture thereof  
A seal ring is provided between a region where a circuit is formed on a semiconductor substrate and a dicing region. The seal ring has a portion where sealing layers of which the cross sectional...
8168895 Printed wiring board  
Provided is a multilayer printed wiring board in which multiple via holes that connect a first power supply wiring with a second power supply wiring are aligned in a line in parallel to a direction...
8169079 Copper interconnection structures and semiconductor devices  
A copper interconnection structure includes an insulating layer, an interconnection body including copper in an opening provided on the insulating layer and a barrier layer including a metal...
8164164 Semiconductor wafer, and semiconductor device formed therefrom  
A semiconductor wafer has a substrate, and a plurality of active areas formed on the substrate. Integrated circuits are formed in the active areas. The semiconductor wafer also has dicing areas...
8164191 Semiconductor device  
A semiconductor device including a semiconductor element and a functional member fixed thereto with an adhesive film is provided, where the performance or reliability degradation due to moisture...
8164190 Structure of power grid for semiconductor devices and method of making the same  
An embodiment of the invention provides a semiconductor structure, which may include a stud of a first conductive material formed inside a dielectric layer; a via of a second conductive material...
8164160 Semiconductor device  
A semiconductor device according to the present invention has a multilayer wiring structure laminating and disposing a plurality of with sandwiching an insulating film and includes: a copper wire...
RE43320 Semiconductor device and manufacturing method thereof  
There is disclosed a semiconductor device comprising a first metal wiring buried in a first wiring groove formed, via a first barrier metal, in a first insulating layer formed on a semiconductor...
8158476 Integrated circuit fabrication  
A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method...
8159070 Chip packages  
Chip assemblies are disclosed that include a semiconductor substrate, multiple devices in and on the semiconductor substrate, a first metallization structure over the semiconductor substrate, and a...
8159057 Semiconductor device and manufacturing method therefor  
The mounting height of a semiconductor device is reduced. A wiring substrate has an upper surface with multiple bonding leads formed therein and a lower surface with multiple lands formed therein....
8159071 Semiconductor package with a metal post  
Disclosed are a semiconductor package and a manufacturing method thereof. The semiconductor package can include a semiconductor substrate, having one surface on which a conductive pad is formed; an...
8154128 3D integrated circuit layer interconnect  
A three-dimensional 3D interconnect structure with a small footprint is described, useful for connection from above to levels of circuit structures in a multi-level device. Also, an efficient and...
8153909 Multilayer wiring board and method of manufacturing the same  
A coreless wiring board has no core board but a laminated structure in which a conductor layer and resin insulating layers are alternately laminated into a multilayer. Each of the resin insulating...
8154124 Semiconductor device having a chip-size package  
A semiconductor chip has a main surface, a back surface and a plurality of side surfaces. A plurality of electrodes is provided on the main surface of the semiconductor chip so as to be arranged in...
8148820 Formed product of line-structured substance composed of carbon element, and method of forming the same  
The present invention proposes a method of readily and reliably forming CNTs independent of a substrate allowing a catalyst metal to deposit thereon, or an underlying material, even for the case...
8143723 Highly integrated and reliable DRAM and its manufacture  
A semiconductor device and its manufacture method wherein the semiconductor substrate has first and second insulating films, the first insulating film being an insulating film other than a silicon...
8143162 Interconnect structure having a silicide/germanide cap layer  
An interconnect structure of an integrated circuit and a method for forming the same are provided. The interconnect structure includes a semiconductor substrate, a low-k dielectric layer over the...
8143724 Standard cell and semiconductor device including the same  
This invention prevents a break in a signal wire disposed between wire ends due to attenuation and improves production yields of devices. In a standard cell, a first signal wire extends in a first...
8143175 Dry etching method  
The invention provides a dry etching method for performing a wiring process on a semiconductor substrate using a plasma etching apparatus, wherein the wiring process is performed without causing...
8143672 Semiconductor device including a metal layer having a first pattern and a second pattern which together form a web structure, thereby providing improved electrostatic discharge protection  
A semiconductor device includes a diode region having a plurality of protection diodes and a pad region overlapped with an upper part of the diode region. The pad region having a pad installed...
8138607 Metal fill structures for reducing parasitic capacitance  
Vertically-staggered-level metal fill structures include inner contiguous metal fill structures and outer contiguous metal fill structures. A dielectric material portion is provided between each...
8134080 Wired circuit board  
A wired circuit board that can provide an enhanced adhesion of a metal supporting board at a marginal portion of an opening formed in the metal supporting board with a simple structure to prevent...
8129843 Methods to mitigate plasma damage in organosilicate dielectrics using a protective sidewall spacer  
Plasma damage in ultra low k dielectric materials during formation of a dual damascene metal interconnect structure is reduced by providing a protective spacer on sidewalls of a line trench. A...
8129833 Stacked integrated circuit packages that include monolithic conductive vias  
Microelectronic packages are fabricated by stacking integrated circuits upon one another. Each integrated circuit includes a semiconductor layer having microelectronic devices and a wiring layer on...
8129842 Enhanced interconnect structure  
The present invention provides a semiconductor interconnect structure with improved mechanical strength at the capping layer/dielectric layer/diffusion barrier interface. The interconnect structure...
8129766 Semiconductor memory device comprising shifted contact plugs  
A memory includes first contact plugs; ferroelectric capacitors above the first contact plugs; second contact plugs in a first interlayer film being below an area which is between two adjacent...
8129761 Contacts for CMOS imagers and method of formation  
Low leakage contacts on leakage sensitive areas of a CMOS imager, such as a floating diffusion region or a photodiode, are disclosed. At least one low leakage polysilicon contact is provided over a...
8125014 Semiconductor device and fabricating method of the same  
Openings are formed by lithography and subsequent dry etching at the portions of a first protective film which correspond to connecting holes of second plugs which will be described later, namely...
8125049 MIM capacitor structure in FEOL and related method  
A capacitor structure includes a semiconductor substrate; a first capacitor plate positioned on the semiconductor substrate, the first capacitor plate including a polysilicon structure having a...
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