Matches 501 - 550 out of 2398 < 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 >
Match Document Document Title
7205649 Ball grid array copper balancing  
A ball grid array device includes a substrate having a first major surface and a second major surface. The first major surface includes leads for electrical connections. The second major surface is...
7205667 Semiconductor device having copper wiring  
A first interlayer insulating film made of insulting material is formed over an underlying substrate. A via hole is formed through the first interlayer insulating film. A conductive plug made of...
7205666 Interconnections having double capping layer and method for forming the same  
Provided are an interconnection of a semiconductor device which includes a capping layer and a method for forming the interconnection. The interconnection of the semiconductor device is a copper...
7205665 Porous silicon undercut etching deterrent masks and related methods  
The disclosed invention relates to masked silicon structures and methods for making porous silicon in selected areas of a silicon substrate via anodic etching. The masked silicon structures...
7202566 Crossed power strapped layout for full CMOS circuit design  
An integrated circuit device and method thereof includes a substrate and a plurality of microelectronic devices. Each of the microelectronics devices includes a patterned feature located over the...
7202565 Semiconductor device which employs an interlayer insulating film of a low mechanical strength and a highly reliable metal pad, and a method of manufacturing the same  
A semiconductor device includes: multiple kinds of interlayer insulating films formed on a semiconductor substrate and having different elastic moduli, respectively; a metal pad arranged on said...
7202567 Semiconductor device and manufacturing method for the same  
A lower interconnection is provided on a semiconductor substrate. A MIM capacitive element is provided on a first interlayer insulation film in which the lower interconnection is buried, and...
7203085 Semiconductor integrated circuit  
First and second internal power source lines supply first and second voltages to an internal circuit, respectively. A first line 31 and a second line 32 are arranged parallel to the first and...
7202157 Method for forming metallic interconnects in semiconductor devices  
A method for forming a metallic interconnect in a semiconductor device is disclosed. An example method forms an IDL on a substrate including predetermined devices, forms a via hole in the IDL,...
7199471 Method and apparatus for reducing capacitive coupling between lines in an integrated circuit  
An integrated circuit ( 78 ) includes a memory circuit ( 10, 110, 210, 310, 410 ) having a group of bitlines ( 21–28, 121–128, 221–228, 321–328, 421–428 ), and having an array of memory...
7199472 Semiconductor device  
In a semiconductor device having the upmost wiring layer comprised of aluminum and the wiring layer immediately below it comprised of copper, the upmost wiring layer is made thicker than the wiring...
7199415 Conductive container structures having a dielectric cap  
Container structures for use in integrated circuits and methods of their manufacture. The container structures have a dielectric cap on the top of a conductive container to reduce the risk of...
7199473 Integrated low-k hard mask  
Embodiments of the invention provide a device with a hard mask layer between first and second ILD layers. The hard mask layer may have a k value approximately equal to the first and/or second ILD...
7196422 Low-dielectric constant structure with a multilayer stack of thin films with pores  
The present invention describes a structure having a multilayer stack of thin films, the thin films being a low-dielectric constant material, the thin films having pores, and a method of forming...
7196426 Multilayered substrate for semiconductor device  
A multilayered substrate for a semiconductor device, which has a multilayered substrate body formed of a plurality sets of a conductor layer and an insulation layer, and having a face for mounting...
7196423 Interconnect structure with dielectric barrier and fabrication method thereof  
An interconnect structure with dielectric barrier and fabrication thereof. The interconnect structure includes a semiconductor substrate and a plurality of stacked structures formed thereon, each...
7196421 Integrated circuit having at least one metallization level  
An integrated circuit is provided that includes at least one metallization level having a plurality of dummy conductors. At least one of the dummy conductors has an oriented shape made up of a...
7196363 Multilayer metal structure of supply rings with large parasitic capacitance  
A multilayer metal supply rings structure of an integrated circuit comprises at least two parallel perimetral metal rails defined in metal layers of different levels, geometrically superposed one...
7193296 Semiconductor substrate  
A semiconductor substrate is partitioned along scribing lines so as to form a plurality of IC regions encompassed by seal rings, wherein a passivation opening is formed in the scribing line in...
7193324 Circuit structure of package substrate  
A circuit structure for a package substrate or a circuit board is provided. The circuit structure has a dielectric layer with an upper surface and a lower surface, at least a first line and at...
7193327 Barrier structure for semiconductor devices  
An opening in a dielectric layer having a unique barrier layer structure is provided. In an embodiment, the opening is a via and a trench. The barrier layer, which may comprise one or more barrier...
7193325 Reliability improvement of SiOC etch with trimethylsilane gas passivation in Cu damascene interconnects  
A method of forming a SiCOH etch stop layer in a copper damascene process is described. A substrate with an exposed metal layer is treated with H 2 or NH 3 plasma to remove metal oxides....
7190077 Semiconductor structure integrated under a pad  
An integrated semiconductor structure has a substrate, a semiconductor element located on the substrate, a pad metal, metal layers located between the pad metal and the substrate, and insulation...
7190043 Techniques to create low K ILD for beol  
One aspect of the present subject matter relates to a method for forming an interlayer dielectric (ILD). In various embodiments of the method, an insulator layer is formed, at least one trench is...
7190052 Semiconductor devices with oxide coatings selectively positioned over exposed features including semiconductor material  
A semiconductor device structure includes a passivation layer through which only non-silicon-comprising structures are exposed. The semiconductor device structure is formed by selectively forming...
7190823 Overlay vernier pattern for measuring multi-layer overlay alignment accuracy and method for measuring the same  
An overlay vernier pattern for measuring multi-layer overlay alignment accuracy and a method for measuring the same is provided. A distance between a first alignment mark in a first material layer...
7190079 Selective capping of copper wiring  
Patterned copper structures are fabricated by selectively capping the copper employing selective etching and/or selective electroplating in the presence of a liner material. Apparatus for...
7187015 High-density metal capacitor using dual-damascene copper interconnect  
An electronic structure having a first conductive layer provided by a dual damascene fabrication process; an etch-stop layer provided by the fabrication process, and electrically coupled with the...
7187084 Damascene method employing composite etch stop layer  
A damascene structure is provided comprising a substrate, a lower intermetal dielectric layer over the substrate, an exposed conductive structure within the lower intermetal dielectric layer, a...
7187085 Semiconductor device including dual damascene interconnections  
A method (and structure) of forming an interconnect on a semiconductor substrate, includes forming a relatively narrow first structure in a dielectric formed on a semiconductor substrate, forming a...
7183625 Embedded MIM capacitor and zigzag inductor scheme  
A new method to form RF devices in the manufacture of an integrated circuit device is achieved. The method comprises providing a substrate. A top metal level is defined overlying the substrate. The...
7183196 Multilayer interconnection board and production method thereof  
A multilayer interconnection board is disclosed that allows reliable electrical connection between an interconnection having a large width and a large area and a via provided in a via hole formed...
7183651 Power plane decoupling  
A system and method for improved power plane decoupling. In a preferred embodiment, two dielectric layers with different dielectric constants are separated by a first conducting layer. Second and...
7183653 Via including multiple electrical paths  
A system includes a device having at least one integrated circuit. The integrated circuit further includes a first layer of conductive material, a second layer of conductive material, and a via...
7180154 Integrated circuit devices having corrosion resistant fuse regions and methods of fabricating the same  
Integrated circuit devices are provided including an integrated circuit substrate and first through fourth spaced apart lower interconnects on the integrated circuit substrate. The third and fourth...
7180120 Semiconductor device having dual stacked MIM capacitor and method of fabricating the same  
Semiconductor devices having a dual stacked MIM capacitor and methods of fabricating the same are disclosed. The semiconductor device includes a dual stacked MIM capacitor formed on the...
7180191 Semiconductor device and method of manufacturing a semiconductor device  
A semiconductor device 200 comprises a SiCN film 202 formed on a semiconductor substrate (not shown), a first SiOC film 204 formed thereon, a SiCN film 208 formed thereon, a second SiOC...
7176569 Semiconductor device and method of manufacturing the same  
Provided is a semiconductor device having a semiconductor chip mounted over a substrate, in which an interconnect is formed, by using an adhesive layer to permit contact conduction between a stud...
7176486 Structure of test element group wiring and semiconductor substrate  
A structure of test element group wiring includes, in addition to an electrode on a substrate including one or more layers of insulating films, and real wirings electrically connected to the...
7176574 Semiconductor device having a multiple thickness interconnect  
A conductive line varies in thickness to assist in overcoming RC delays and noise coupling. By varying line thickness, variation in conductor width is avoided if necessary to maintain a specified...
7176573 Semiconductor device with a multi-level interconnect structure and method for making the same  
A semiconductor device includes a semiconductor die and a multi-level interconnect structure that has a first insulating layer formed on the die, conductive horizontal bodies, each of which is...
7175970 Mechanically robust interconnect for low-k dielectric material using post treatment  
In an embodiment, a trench is formed above a via from a photo resist (PR) trench pattern in a dielectric layer. The trench is defined by two sidewall portions and base portions. The base portions...
7173337 Semiconductor device manufactured by the damascene process having improved stress migration resistance  
A semiconductor device including a second insulating film formed on a substantially flat surface, on which a surface of a first wiring and a surface of a first insulating film are continued, to...
7170178 Capacitive integrated circuit structure  
A capacitive structure is provided that includes secondary stacks of superposed secondary electrodes that each include transverse branches connected via a longitudinal branch, means for connecting...
7170148 Semi-fusible link system for a multi-layer integrated circuit and method of making same  
A semi-fusible link system and method for a multi-layer integrated circuit including active circuitry on a first layer having a metal one layer including a semi-fusible link element on a second...
7170173 Magnetically lined conductors  
A conductor with improved magnetic field per current ratio is disclosed. The conductor includes a magnetic liner lining a second surface and sides thereof. The corners of the conductor where the...
7170177 Semiconductor apparatus  
A disclosed semiconductor apparatus includes a substrate, a first insulating layer formed on the substrate, the first insulating layer including a Cu wiring part, and a second insulating layer...
7170174 Contact structure and contact liner process  
A contact structure and a method of forming thereof for semiconductor devices or assemblies are described. The method provides process steps to create a contact structure encompassed by a...
7166922 Continuous metal interconnects  
A method of forming an interconnection that includes introducing a barrier material in a via of a dielectric to a circuit device on a substrate in such a manner to deposit the barrier material on...
7166923 Semiconductor device, electro-optical unit, and electronic apparatus  
The invention provides a semiconductor device that allows high-scale integration of a pattern layout to reduce the pitch of wiring lines without changing a design rule, and to provide an...
Matches 501 - 550 out of 2398 < 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 >