Matches 451 - 500 out of 2398 < 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 >
Match Document Document Title
7247951 Chip carrier with oxidation protection layer  
A chip carrier comprising a laminated layer and an oxidation protection layer is provided. The oxidation protection layer is a non-electrolytic metallic coating or an organic oxidation protection...
7247556 Control of wafer warpage during backend processing  
A method of fabricating an integrated circuit (IC), during which wafer warpage is controlled by appropriately controlling intrinsic stresses in one or more service layers of the layer stack of the...
7247939 Metal filled semiconductor features with improved structural stability  
A method for forming a metal filled semiconductor feature with improved structural stability including a semiconductor wafer having an anisotropically etched opening formed through a plurality of...
7247894 Very fine-grain voltage island integrated circuit  
Methods of supplying voltages to integrated circuits are provided. A high voltage VddH and/or a low voltage VddL can be supplied to a filler cell and routed to other cells. Each of the VddH and...
7247902 Semiconductor device and method of manufacturing the same  
A semiconductor device comprises a first metal layer, which comprises a buried metal layer connected to a diffusion layer within a substrate or to a lower-layer wiring. A first metal wiring layer,...
7245016 Circuit layout structure  
A circuit layout structure for a chip is provided. The chip has a bonding pad area, a nearby device area, and a substrate. The circuit layout structure essentially comprises a plurality of circuit...
7243424 Production method for a multilayer ceramic substrate  
An object of the invention is to connect different dielectrics electrically to each other in the direction of main surface of a sheet in a multilayer ceramic substrate and to increase the degree of...
7245017 Liquid discharge head and manufacturing method thereof  
The liquid discharge head has a three-dimensional structure which defines a space including a pressure chamber filled with liquid and a flow channel for supplying the liquid to the pressure...
7244673 Integration film scheme for copper / low-k interconnect  
A structure for a multi-level interconnect inter-level dielectric layer (ILD), a method of manufacturing thereof, and a semiconductor device including the ILD layer. The ILD layer includes a first...
7242094 Semiconductor device having capacitor formed in multilayer wiring structure  
A semiconductor device having a capacitor formed in a multilayer wiring structure, the semiconductor device comprising a multilayer wiring structure including a plurality of wiring layers formed on...
7242095 Semiconductor device having a dummy pattern  
A semiconductor device includes a substrate, a circuit pattern formed on the substrate, and a plurality of dummy patterns formed on the substrate in addition to the circuit pattern, wherein the...
7241682 Method of forming a dual damascene structure  
An improved method of forming an integrated circuit that includes a dual damascene interconnect is described. A contact via hole is formed in a dielectric layer disposed above a semiconductor...
7242099 Chip package with multiple chips connected by bumps  
A method of assembling chips. A first chip and a second chip are provided. At least one conductive pillar is formed on the first chip, and a conductive connecting material is formed on the...
7242025 Radiation emitting semiconductor component having a nitride compound semiconductor body and a contact metallization layer on its surface  
A radiation-emitting semiconductor component has a semiconductor body containing a nitride compound semiconductor, and a contact metallization layer disposed on a surface of the semiconductor body....
7241683 Stabilized photoresist structure for etching process  
A method for forming features in an etch layer is provided. A first mask is formed over the etch layer where the first mask defines a plurality of spaces with widths. The first mask is laterally...
7239337 Combined semiconductor apparatus with thin semiconductor films  
A semiconductor apparatus includes two thin semiconductor films bonded to a substrate, and a thin-film interconnecting line electrically connecting a semiconductor device in the first thin...
7238980 Semiconductor device having plural electroconductive plugs  
The short circuit between the bit line and thee cell contact can be prevented without considerably increasing the number of the manufacturing processes. The bit line 6 electrically coupled to the...
7239018 Composition for forming a porous film prepared by hydrolysis and condensation of an alkoxysilane using a trialkylmethylammonium hydroxide catalyst  
Provided is a composition formed by hydrolysis and condensation composition of the alkoxysilane, the composition comprising a reduced amount of metallic and halogen impurities and being applicable...
7239002 Integrated circuit device  
In a temperature sensor section of a semiconductor integrated circuit device, first vias of tungsten are formed at the topmost layer of a multi-layer wiring layer and pads of titanium are provided...
7239005 Semiconductor device with bypass capacitor  
A semiconductor device comprises a semiconductor substrate having first and second active regions of first conductivity type, first and second insulated electrodes crossing the first and second...
7239019 Selectively converted inter-layer dielectric  
An inter-layer dielectric structure and method of making such structure are disclosed. A composite dielectric layer, initially comprising a porous matrix and a porogen, is formed. Subsequent to...
7236385 Memory architecture  
A DDR SDRAM where unidirectional row logic is associated with and connected to a single memory array instead of being associated with and connected to multiple memory arrays. The unidirectional row...
7235882 Semiconductor device having a wiring layer of damascene structure and method for manufacturing the same  
In a semiconductor device, a wiring pattern groove is formed in a surface portion of a silicon oxide film provided above a semiconductor substrate. A wiring layer is buried into the wiring pattern...
7232746 Method for forming dual damascene interconnection in semiconductor device  
A method for forming a dual damascene interconnection in a semiconductor device, which is capable of preventing a lower metal film from being corroded. The method includes the steps of forming an...
7233052 Semiconductor device including fine dummy patterns  
A semiconductor device of this invention includes a first interconnect pattern formed on a semiconductor substrate and a second interconnect pattern formed above the first interconnect pattern with...
7233070 Semiconductor device having no cracks in one or more layers underlying a metal line layer and method of manufacturing the same  
A semiconductor device and a method of manufacturing the same which yields high reliability and a high manufacturing yield. The semiconductor device includes a metal line layer having a plurality...
7230337 Semiconductor device including ladder-shaped siloxane hydride and method for manufacturing same  
The present invention reduces the effective dielectric constant of the interlayer insulating film while inhibiting the decrease of the reliability of the semiconductor device, which otherwise is...
7230336 Dual damascene copper interconnect to a damascene tungsten wiring level  
A method and structure for fabricating a dual damascene copper interconnect which electrically contacts a damascene tungsten wiring level. The method forms a first layer on a semiconductor...
7227244 Integrated low k dielectrics and etch stops  
A method of depositing and etching dielectric layers having low dielectric constants and etch rates that vary by at least 3:1 for formation of horizontal interconnects. The amount of carbon or...
7227255 Semiconductor device and method of producing the same  
A semiconductor device enabling word lines to be arranged at close intervals, comprising a plurality of memory transistors arranged in an array and a plurality of word lines serving also as gate...
7224060 Integrated circuit with protective moat  
A method of manufacturing an integrated circuit provides a substrate having a semiconductor device, and includes forming an intermetal dielectric layer over the substrate and the semiconductor...
7224068 Stable metal structure with tungsten plug  
In the preferred embodiment, a thick regular-k dielectric is formed on a substrate. A tungsten plug is formed in the thick regular-k dielectric. The thick regular-k dielectric is recessed and a...
7224064 Semiconductor device having conductive interconnections and porous and nonporous insulating portions  
A semiconductor device and manufacturing method, wherein the semiconductor device has a semiconductor substrate on which a plurality of elements constituting a logic type device have been formed; a...
7224063 Dual-damascene metallization interconnection  
An interconnect structure, comprising: a lower level wire having a side and a bottom, the lower level wire comprising: a lower core conductor and a lower conductive liner, the lower conductive...
7223630 Low stress semiconductor device coating and method of forming thereof  
A low stress, protective coating for a semiconductor device and a method for its manufacture. A preferred embodiment comprises coating the top surface of a semiconductor die with polyimide except...
7221034 Semiconductor structure including vias  
A semiconductor device may comprise a semiconductor substrate having a top and a bottom surface, first and second insulating layer deposited on the top surface of the substrate, a runner arranged...
7221050 Substrate having a functionally gradient coefficient of thermal expansion  
A substrate and a method of making a substrate having a functionally gradient coefficient of thermal expansion are described herein. A system having a silicon die, an organic package substrate, and...
7217963 Semiconductor integrated circuit device  
In a low power consumption mode in which prior data is retained upon power shutdown, the return speed thereof is increased. While use of an existent data retaining flip-flop may be considered, this...
7217370 Wiring board and process for producing the same  
A wiring board with microstrip structure has: a first conductor layer that is provided with conductor wirings to be connected to a semiconductor chip in its external terminal (bonding pad); a...
7215000 Selectively encased surface metal structures in a semiconductor device  
The present invention provides, in one embodiment, An integrated circuit device ( 100 ). The integrated circuit device ( 100 ) comprises a circuit feature ( 105 ) located over a semiconductor...
7215029 Multilayer interconnection structure of a semiconductor  
In order to solve the aforementioned problems, the present-invention provides a semiconductor device having a multilayer interconnection structure, wherein an upper interconnection comprises a...
7211897 Semiconductor device and method for fabricating the same  
The semiconductor device comprises on a semiconductor substrate an insulating structure formed of a plurality of insulating films; an interconnection structure buried in the insulating structure...
7208836 Integrated circuitry and a semiconductor processing method of forming a series of conductive lines  
A semiconductor processing method of forming a plurality of conductive lines includes, a) providing a substrate; b) providing a first conductive material layer over the substrate; c) providing a...
7208843 Routing design to minimize electromigration damage to solder bumps  
A novel pad structure for an integrated circuit component that utilizes a bump interconnect for connection to other integrated circuit components that produces a relatively uniform current...
7208831 Semiconductor device having multilayer wiring structure and method, wherein connecting portion and wiring layer are formed of same layer  
A method for manufacturing a semiconductor device includes a step of forming a first groove in a first insulating film, forming a conductive film in the first groove, a step of selectively forming...
7205650 Composite devices of laminate type and processes  
In a composite device of the laminate type having a laminate structure of a composite ceramic layer and a dielectric ceramic layer, the composite ceramic layer including a layer portion having the...
7205566 Transistor-level signal cutting method and structure  
A modifiable circuit structure and its method of formation are disclosed. The modifiable circuit structure electrically couples one portion of an interconnect with another portion of the...
7205637 Semiconductor device with a multilevel interconnection connected to a guard ring and alignment mark  
A semiconductor device includes an alignment mark which is arranged adjacent to each corner of a semiconductor chip, and a plug which contacts the alignment mark. The alignment mark is formed by...
7205668 Multi-layer printed circuit board wiring layout  
A multi-layer printed circuit board (PCB) includes a first wire layer, a middle layer above the first wire layer, a second wire layer above the middle layer, and a slanting via formed in the middle...
7205486 Thermally isolated via structure  
This document discusses, among other things, a flexible circuit or other laminate comprising a first conductive layer and a second conductive layer disposed over the first conductive layer. An...
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