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7414314 Semiconductor device and manufacturing method thereof  
A semiconductor device has a semiconductor substrate, a first insulating film formed on a surface of the semiconductor substrate, a first recess formed in the first insulating film, a first barrier...
7414275 Multi-level interconnections for an integrated circuit chip  
Multilevel metallization layouts for an integrated circuit chip including transistors having first, second and third elements to which metallization layouts connect. The layouts minimize current...
7397122 Metal wiring for semiconductor device and method for forming the same  
A metal wiring for a semiconductor device and a method for forming the same are provided. The metal wiring includes a first insulating layer and a second insulating layer; an interlayer insulating...
7371679 Semiconductor device with a metal line and method of forming the same  
A method of forming a metal line in a semiconductor device including forming an inter-metal dielectric (IMD) layer on the semiconductor substrate including the predetermined pattern, planarizing...
7348676 Semiconductor device having a metal wiring structure  
After an insulation layer is formed on a substrate, a contact hole is formed through the insulation layer. A recessed plug is formed to partially fill up the contact hole. The recessed plug has a...
7338907 Selective etching processes of silicon nitride and indium oxide thin films for FeRAM device applications  
A dry etch process is described for selectively etching silicon nitride from conductive oxide material for use in a semiconductor fabrication process. Adding an oxidant in the etch gas mixture...
7332813 Semiconductor device  
A semiconductor device with a metallic region can have a resistance to stress migration and increased reliability. A lower layer wiring made from a barrier metal film ( 102 ) and a copper...
7327034 Compositions for planarization of metal-containing surfaces using halogens and halide salts  
A planarization method includes providing a metal-containing surface (preferably, a Group VIII metal-containing surface, and more preferably a platinum-containing surface) and positioning it for...
7315082 Semiconductor device having integrated circuit contact  
A process for forming vertical contacts in the manufacture of integrated circuits, and devices so manufactured, is disclosed. The process eliminates the need for precise mask alignment and allows...
7294570 Contact integration method  
A method of making a contact plug and a metallization line structure is disclosed in which a substrate is provided with at least one contact hole within an insulation layer situated on a...
7291920 Semiconductor structures  
In one aspect, the invention includes a method of forming a roughened layer of platinum, comprising: a) providing a substrate within a reaction chamber; b) flowing an oxidizing gas into the...
7259432 Semiconductor device for reducing parasitic capacitance produced in the vicinity of a transistor located within the semiconductor device  
A semiconductor device includes: a gate electrode formed on a substrate; impurity regions formed in the substrate and to both sides of the gate electrode; a first interlayer insulating film formed...
7250682 Semiconductor integrated circuit device  
Interconnections are formed over an interlayer insulating film which covers MISFETQ 1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a...
7235882 Semiconductor device having a wiring layer of damascene structure and method for manufacturing the same  
In a semiconductor device, a wiring pattern groove is formed in a surface portion of a silicon oxide film provided above a semiconductor substrate. A wiring layer is buried into the wiring pattern...
7233059 Semiconductor arrangement  
The invention relates to a vertical arrangement of at least two semiconductor components which are electrically insulated from one another by at least one passivation layer. The invention likewise...
7230335 Inspection methods and structures for visualizing and/or detecting specific chip structures  
The present invention provides inspection methods and structures for facilitating the visualization and/or detection of specific chip structures. Optical or fluorescent labeling techniques are used...
7227265 Electroplated copper interconnection structure, process for making and electroplating bath  
Interconnect structures with copper conductors being at least substantially free of internal seams or voids are obtained employing an electroplating copper bath containing dissolved cupric salt...
7193323 Electroplated CoWP composite structures as copper barrier layers  
A composite material comprising a layer containing copper, and an electrodeposited CoWP film on the copper layer. The CoWP film contains from 11 atom percent to 25 atom percent phosphorus and has a...
7187085 Semiconductor device including dual damascene interconnections  
A method (and structure) of forming an interconnect on a semiconductor substrate, includes forming a relatively narrow first structure in a dielectric formed on a semiconductor substrate, forming a...
7180188 Contact structure of semiconductor devices and method of fabricating the same  
A contact structure includes a lower conductive pattern disposed on a predetermined region of a semiconductor substrate. The lower conductive layer has a concave region at a predetermined region of...
7176571 Nitride barrier layer to prevent metal (Cu) leakage issue in a dual damascene structure  
A method for forming a composite barrier layer that also functions as an etch stop in a damascene process is disclosed. A SiC layer is deposited on a substrate in a CVD process chamber followed by...
7164206 Structure in a microelectronic device including a bi-layer for a diffusion barrier and an etch-stop layer  
The invention relates to a microelectronic device and a structure therein that includes a diffusion barrier layer having a first thickness and a first dielectric constant. An etch stop layer is...
7161246 Interconnect alloys and methods and apparatus using same  
Integrated circuit interconnect alloys having copper, silver or gold as the major constituent element. The resulting reduction in melting temperature allows for improved coverage of high aspect...
7146722 Method of forming a bond pad structure  
A bond pad structure comprising two bond pads, methods of forming the bond pad structure, an integrated circuit die incorporating the bond pad structure, and methods of using the bond pad structure...
7145245 Low-k dielectric film with good mechanical strength that varies in local porosity depending on location on substrate—therein  
The present invention discloses a method including providing a substrate; forming a dielectric over the substrate, the dielectric having a k value of about 2.5 or lower, the dielectric having a...
7145244 Hardening of copper to improve copper CMP performance  
A method for reducing the topography from CMP of metal layers during the semiconductor manufacturing process is described. Small amounts of solute are introduced into the conductive metal layer...
7145239 Circuit board with trace configuration for high-speed digital differential signaling  
Trace configurations for carrying high-speed digital differential signals provide for reduced conduction loss and improved signal integrity. In one embodiment, a circuit board has a first set of...
7145238 Semiconductor package and substrate having multi-level vias  
A semiconductor package and substrate having multi-level plated vias provide a high density blind via solution at low incremental cost. Via are half-plated atop a circuit pattern and then a second...
RE39413 Low friction polish-stop stratum for endpointing chemical-mechanical planarization processing of semiconductor wafers  
The present invention is a semiconductor wafer that enhances polish-stop endpointing in chemical-mechanical planarization processes. The semiconductor wafer has a substrate with a device feature...
7122898 Electrical programmable metal resistor  
The present invention provides an electrical programmable metal resistor and a method of fabricating the same in which electromigration stress is used to create voids in the structure that increase...
7115991 Method for creating barriers for copper diffusion  
A barrier layer for a semiconductor device is provided. The semiconductor device comprises a dielectric layer, an electrically conductive copper containing layer, and a barrier layer separating the...
7105925 Differential planarization  
Method and structure for optimizing and controlling chemical mechanical planarization are disclosed. Embodiments of the invention include planarization techniques to make nonplanar surfaces...
7098497 Semiconductor device using high-dielectric-constant material and method of manufacturing the same  
A semiconductor device includes a MOS transistor, interlayer dielectric film, first and second high-dielectric-constant films, and first and second conductive films. The MOS transistor is formed on...
7087998 Control of air gap position in a dielectric layer  
A method for controlling the position of air gaps in intermetal dielectric layers between conductive lines and a structure formed using such a method. A first dielectric layer is deposited over at...
7071099 Forming of local and global wiring for semiconductor product  
Methods of forming different back-end-of-line (BEOL) wiring for different circuits on the same semiconductor product, i.e., wafer or chip, are disclosed. In one embodiment, the method includes...
7042099 Semiconductor device containing a dummy wire  
There is disclosed a semiconductor device comprising a substrate, a first insulating film which is provided above the substrate and has a relative dielectric constant which is at most a...
7041586 Semiconductor device having a multilayer interconnection structure  
A semiconductor device includes a multilayer interconnection structure including an organic interlayer insulation film in which a conductor pattern is formed by a damascene process, wherein the...
7034360 High voltage transistor and method of manufacturing the same  
Provided is a high voltage transistor in a flash memory device comprising: a source/drain junction of a DDD structure consisting of a high-concentration impurity region and a low-concentration...
7015531 FeRAM having bottom electrode connected to storage node and method for forming the same  
A FeRAM device in which a bottom electrode of a ferroelectric capacitor is connected to a source/drain region of a transistor and a top electrode is connected to a plate line. The FeRAM device...
7012335 Semiconductor device wiring and method of manufacturing the same  
A wiring of a semiconductor device and a method of manufacturing the same are disclosed. A first conductive layer is formed on a semiconductor substrate followed by a first insulation material...
6992390 Liner with improved electromigration redundancy for damascene interconnects  
An interconnection structure for semiconductor integrated circuits is disclosed. The interconnection structure comprises a redundant layer, and at least one adhesion/diffusion barrier layer. The...
6992371 Device including an amorphous carbon layer for improved adhesion of organic layers and method of fabrication  
A novel device, such as a semiconductor device, a microfluidic device, a surface acoustic wave device an imprint template, or the like, including an amorphous carbon layer for improved adhesion of...
6979903 Integrated circuit with dielectric diffusion barrier layer formed between interconnects and interlayer dielectric layers  
An integrated circuit is provided having a semiconductor substrate with a semiconductor device. A dielectric layer formed over the semiconductor substrate has an opening provided therein. The...
6972492 Method and structure to form capacitor in copper damascene process for integrated circuit devices  
A method and resulting structure of forming a metal on metal capacitor structure for an integrated circuit device, e.g., mixed signal. The method includes forming a dual damascene structure, where...
6969911 Wiring structure of semiconductor device and production method of the device  
In a wiring structure of a semiconductor device, dielectric tolerance of the wiring is improved by preventing diffusion of the wiring material. The wiring structure of the semiconductor device...
6960834 Semiconductor device having multi-layer interconnection structure and method of manufacturing the same  
A semiconductor device includes a foundation having a first conductive region, and an inter-connection layer provided separate from the foundation. A first region occupying a range from the...
6952051 Interlevel dielectric structure  
An interlevel dielectric structure includes first and second dielectric layers between which are located lines of a conductive material with a dielectric material in spaces between the lines of...
6952044 Monolithic bridge capacitor  
According to the most preferred embodiments of the present invention, at least one of the two plates of a capacitor is formed in at least two different layers of an integrated circuit. The methods...
6940171 Multi-layer dielectric and method of forming same  
A multiple dielectric device and its method of manufacture overlaying a semiconductor material, including a substrate, an opening relative to the substrate, the opening having an aspect ratio...
6940170 Techniques for triple and quadruple damascene fabrication  
The present invention provides integrated circuit fabrication methods and devices wherein triple damascene structures are formed in five consecutive dielectric layers ( 312, 314, 316, 318 and 320...
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