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Match Document Document Title
7446416 Barrier material formation in integrated circuit structures  
A method of forming an electrically conductive via. A first electrically conductive layer is formed, and a second layer is formed on the first layer. The second layer has desired barrier layer...
7446415 Method for filling electrically different features  
Methods of electroless filling electrically different features such as contact openings to form interconnects and conductive contacts, and semiconductor devices, dies, and systems that incorporate...
7443020 Minimizing number of masks to be changed when changing existing connectivity in an integrated circuit  
Dummy stacks, each providing a common point of connectivity potentially across all metal layers, are incorporated along with the functional block in an integrated circuit. When the connectivity of...
7439176 Semiconductor device multilayer structure, fabrication method for the same, semiconductor device having the same, and semiconductor device fabrication method  
In one embodiment, a semiconductor device comprises a semiconductor substrate and a doped conductive layer formed over the semiconductor substrate. A diffusion barrier layer is formed over the...
7435670 Bit line barrier metal layer for semiconductor device and process for preparing the same  
The present invention relates to a bit line barrier metal layer for a semiconductor device and a process for preparing the same, the process comprising: forming bit line contact on an insulation...
7432192 Post ECP multi-step anneal/H2 treatment to reduce film impurity  
A method of forming a copper interconnect in a dual damascene scheme is described. After a diffusion barrier layer and seed layer are sequentially formed on the sidewalls and bottoms of a trench...
7423345 Semiconductor constructions comprising a layer of metal over a substrate  
The invention includes a method of forming a metal-containing film over a surface of a semiconductor substrate. The surface is exposed to a supercritical fluid. The supercritical fluid has H 2 , at...
7422977 Copper adhesion improvement device and method  
A semiconductor device, in which a semiconductor integrated circuit having a multi-level interconnection structure is formed, according to an embodiment of the present invention, comprises a copper...
7420275 Boron-doped SIC copper diffusion barrier films  
Copper diffusion barrier films having a boron-doped silicon carbide layer with at least 25% boron by atomic weight of the layer composition have advantages for semiconductor device integration...
7417264 Top-emitting nitride-based light emitting device and method of manufacturing the same  
Provided are a top-emitting N-based light emitting device and a method of manufacturing the same. The device includes a substrate, an n-type clad layer, an active layer, a p-type clad layer, and a...
7414314 Semiconductor device and manufacturing method thereof  
A semiconductor device has a semiconductor substrate, a first insulating film formed on a surface of the semiconductor substrate, a first recess formed in the first insulating film, a first barrier...
7411301 Semiconductor integrated circuit device  
In a semiconductor integrated circuit device having plural layers of buried wirings, it is intended to prevent the occurrence of a discontinuity caused by stress migration at an interface between a...
7411300 Agglomeration control using early transition metal alloys  
Structures and methods of fabricating portions of integrated circuit devices to reduce agglomeration tendencies of high surface-energy metals used in interconnects and contacts. Early transition...
7411299 Passivation film of semiconductor device  
Disclosed are a method of manufacturing a semiconductor device and a structure of a semiconductor device. A method of forming a passivation film of a semiconductor device comprises the steps of...
7411214 High performance FET devices and methods thereof  
Structure and methods of fabrication are disclosed for an enhanced FET devices in which dopant impurities are prevented from diffusing through the gate insulator. The structure comprises a Si:C, or...
7405481 Glue layer for adhesion improvement between conductive line and etch stop layer in an integrated circuit chip  
In an integrated circuit chip, a conductive line is formed in a first IMD layer. The conductive line is formed of a conductive line material that tends to form an oxide when exposed to an...
7404247 Method for making a pressure sensor  
A method for making a pressure sensor including the steps of providing a substrate and forming or locating a pressure sensing component on the substrate. The method further includes the step of,...
7402883 Back end of the line structures with liner and noble metal layer  
A back end of the line (BEOL) structure of a semiconductor device is presented. In one embodiment, the structure may include a first liner layer disposed on an intermediate interconnect structure,...
7400043 Semiconductor constructions  
The invention includes a method of forming a metal-containing film over a surface of a semiconductor substrate. The surface is exposed to a supercritical fluid. The supercritical fluid has H 2 , at...
7394157 Integrated circuit and seed layers  
Structures are provided which improve performance in integrated circuits. The structures include a diffusion barrier and a seed layer in an integrated circuit both formed using a low energy ion...
7394154 Embedded barrier for dielectric encapsulation  
A semiconductor interconnect structure and method providing an embedded barrier layer to prevent damage to the dielectric material during or after Chemical Mechanical Polishing. The method employs...
7390739 Formation of a masking layer on a dielectric region to facilitate formation of a capping layer on electrically conductive regions separated by the dielectric region  
A masking layer is formed on a dielectric region of an electronic device so that, during subsequent formation of a capping layer on electrically conductive regions of the electronic device that are...
7388290 Spacer patterned, high dielectric constant capacitor and methods for fabricating the same  
A high dielectric constant memory cell capacitor and method for producing the same, wherein the memory cell capacitor utilizes relatively large surface area conductive structures of thin spacer...
7388289 Local multilayered metallization  
An interconnect comprises a trench and a number of metal layers above the trench. The trench has a depth and a width. The depth is greater than a critical depth, and the number of metal layers is a...
7385294 Semiconductor device having nickel silicide and method of fabricating nickel silicide  
A semiconductor device having nickel silicide and a method for fabricating nickel silicide. A semiconductor substrate having a plurality of doped regions is provided. Subsequently, a nickel layer...
7385259 Method of manufacturing a multilayered doped conductor for a contact in an integrated circuit device  
A method of manufacturing a memory device addressing reliability and refresh characteristics through the use of a multilayered doped conductor, and a method making is described. The multilayered...
7381643 Wiring structure forming method and semiconductor device  
After a via hole ( 102 ) to connect a lower wiring ( 101 ) and an upper wiring not shown is formed in an insulating film ( 103 ) using an etching stopper film ( 104 ) and a hard mask ( 105 ), a...
7372160 Barrier film deposition over metal for reduction in metal dishing after CMP  
A protective barrier layer, formed of a material such as titanium or titanium nitride for which removal by chemical mechanical polishing (CMP) is primarily mechanical rather than primarily...
7372153 Integrated circuit package bond pad having plurality of conductive members  
An integrated circuit package bond pad includes an insulating layer and an electrode located over the insulating layer. The electrode has a first surface configured to be bonded to external...
7372152 Copper interconnect systems  
An integrated circuit (IC) may include a substrate, a first dielectric layer adjacent the substrate, and at least one trench in the first dielectric layer. The IC may also include a metal liner...
7365430 Semiconductor device and method of manufacturing the same  
Disclosed herein is a semiconductor device and method of manufacturing the same. A step between a memory cell formed in a cell region and a transistor formed in a peripheral circuit region is...
7361992 Semiconductor device including interconnects formed by damascene process and manufacturing method thereof  
After etching the interlayer dielectric film 4 formed on the lower layer interconnect line 1 into a shape with holes, the upper layer dielectric film 6 is etched into a shape with trenches...
7361991 Closed air gap interconnect structure  
A closed air gap interconnect structure is described. The structure includes discrete regions of a permanent support dielectric under the interconnect lines so that the lines are substantially...
7358589 Amorphous carbon metal-to-metal antifuse with adhesion promoting layers  
A metal-to-metal antifuse having a lower metal electrode, a lower thin adhesion promoting layer disposed over the lower metal electrode, an amorphous carbon antifuse material layer disposed over...
7352053 Insulating layer having decreased dielectric constant and increased hardness  
A method of manufacturing a mechanically robust insulating layer, including forming a low-k dielectric layer having a first dielectric constant on a substrate and forming a carbon nitride cap layer...
7348676 Semiconductor device having a metal wiring structure  
After an insulation layer is formed on a substrate, a contact hole is formed through the insulation layer. A recessed plug is formed to partially fill up the contact hole. The recessed plug has a...
7348648 Interconnect structure with a barrier-redundancy feature  
An interconnect structure that includes a barrier-redundancy feature which is capable of avoiding a sudden open circuit after an electromigration (EM) failure as well as a method of forming the...
7348590 Phase change memory cell with high read margin at low power operation  
A memory cell device includes a first electrode, a heater adjacent the first electrode, phase-change material adjacent the heater, a second electrode adjacent the phase-change material, and...
7341908 Semiconductor device and method of manufacturing the same  
Provided are a semiconductor device including a reliable interconnect and a method of manufacturing the same. The semiconductor device includes a substrate, an inter-metal dielectric (IMD) pattern...
7335990 Process of forming a composite diffusion barrier in copper/organic low-k damascene technology  
A semiconductor device, having a composite barrier layer, comprising the following. A substrate has a dielectric layer formed thereover and having an opening within the dielectric layer. The...
7335989 Semiconductor device and production method therefor  
A semiconductor device provided with: a first interconnection layer provided on a semiconductor substrate; an interlevel insulation film provided over the first interconnection layer; a barrier...
7332813 Semiconductor device  
A semiconductor device with a metallic region can have a resistance to stress migration and increased reliability. A lower layer wiring made from a barrier metal film ( 102 ) and a copper...
7332428 Metal interconnect structure and method  
In a method of fabricating a semiconductor device, a dielectric layer is formed over a conductive region. A dual damascene structure including a trench and a via is formed within the dielectric...
7329952 Method of fabricating a semiconductor device  
The semiconductor device comprises a copper interconnection 26 b buried in an insulating film 16 , and a dummy pattern for chemical mechanical polishing buried in the insulating film 16 near...
7327033 Copper alloy via bottom liner  
Improved mechanical and adhesive strength and resistance to breakage of copper integrated circuit interconnections is obtained by forming a copper alloy in a copper via/wiring connection in an...
7327031 Semiconductor device and method of manufacturing the same  
There is provided a solution to the problem of the poor adhesion in the pad portion while inhibiting the dishing in the pad portion. An SiON film, which covers insulating areas and has an opening...
7323737 DRAM constructions and electronic systems  
The invention includes methods in which metal oxide dielectric materials are deposited over barrier layers. The barrier layers can comprise compositions of metal and one or more of carbon, boron...
7321171 Semiconductor integrated circuit device  
A barrier layer and a copper film are successively formed on a silicon oxide film including a groove for wiring in the silicon oxide film and a silicon nitride film, both formed on a semiconductor...
7319270 Multi-layer electrode and method of forming the same  
An interconnect includes an opening formed in a dielectric layer. A conductive barrier is deposited in the opening, over which a first conductive layer is deposited. A conductive oxide is deposited...
7312488 Semiconductor storage device and manufacturing method for the same  
There is provided a semiconductor storage device comprising a ferroelectric capacitor superior in barrier capability against penetration of hydrogen from all directions including a transverse...
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