Matches 1 - 50 out of 971 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >
Match Document Document Title
7612453 Semiconductor device having an interconnect structure and a reinforcing insulating film  
A semiconductor device includes in an interconnect structure which includes a first interconnect made of a copper-containing metal, a first Cu silicide layer covering the upper portion of the first...
7602063 Semiconductor device and manufacturing method therefor  
In a semiconductor having a multilayer wiring structure device on a semiconductor substrate, the multilayer wiring structure includes an interlayer insulating film having at least an organic...
7595554 Interconnect structure with dielectric air gaps  
An interconnect structure with improved performance and capacitance by providing air gaps inside the dielectric layer by use of a multi-phase photoresist material. The interconnect features are...
7589398 Embedded metal features structure  
A method and structure for creating embedded metal features includes embedded trace substrates wherein bias and signal traces are embedded in a first surface of the embedded trace substrate and...
7586195 Semiconductor device  
An electronic component for microwave transmission includes a high resistivity substrate on which is at least located several metallization layers divided into portions. A first set of piled up...
7582966 Semiconductor chip and method for fabricating the same  
A semiconductor chip includes a silicon substrate, a first dielectric layer over said silicon substrate, a metallization structure over said first dielectric layer, wherein said metallization...
7575994 Semiconductor device and manufacturing method of the same  
The invention provides a CSP type semiconductor device with high reliability. The semiconductor device includes a pad electrode formed on a semiconductor substrate, a first passivation film...
7573132 Wiring structure of a semiconductor device and method of forming the same  
A wiring structure of a semiconductor device may have an insulation layer, a spacer and a plug. The insulation layer may be provided on a substrate and may have an opening through which a contact...
7566976 Semiconductor device and method for fabricating the same  
A semiconductor device has a porous low-dielectric-constant film formed on a substrate and having an opening and a fine particle film composed of a plurality of aggregately deposited fine particles...
7566971 Semiconductor device and manufacturing method thereof  
The invention provides a technology for manufacturing a higher performance and higher reliability semiconductor device at low cost and with high yield. The semiconductor device of the invention has...
7566964 Aluminum pad power bus and signal routing for integrated circuit devices utilizing copper technology interconnect structures  
An integrated circuit device structure and a process for fabricating the structure wherein the power bus interconnect structure is formed in the aluminum pad or contact layer. An interconnect...
7564133 Semiconductor device and method for fabricating the same  
A semiconductor device comprises: a lower interconnect formed over a semiconductor substrate; an insulating film formed on the lower interconnect; a via hole penetrating the insulating film to...
7564132 Semiconductor chip  
A semiconductor chip 100 includes a semiconductor substrate (not shown), and a stacked film 150 formed over the semiconductor substrate, which includes carbon-containing insulating films such...
7557453 Semiconductor device, method of manufacturing a semiconductor device and substrate to be used to manufacture a semiconductor device  
A semiconductor device comprises a first electrode-lead having a first Au film, a first Ni film, a Cu film, a second Au film and a second Ni film stacked in order, a second electrode-lead having a...
7553739 Integration control and reliability enhancement of interconnect air cavities  
An improved semiconductor device, integrated circuit, and integrated circuit fabrication method introduce highly controlled air cavities within high-speed copper interconnects. A polymer material...
7550855 Vertically spaced plural microsprings  
A plurality of vertically spaced-apart microsprings are provided to increase microspring contact force, contact area, contact reliability, and contact yield. The microspring material is deposited,...
7550849 Conductive structures including titanium-tungsten base layers  
Methods may be provided for forming an electronic device including a substrate, a conductive pad on the substrate, and an insulating layer on the substrate wherein the insulating layer has a via...
7547916 Electronic circuit  
An electronic circuit formed on an insulating substrate and having thin-film transistors (TFTs) comprising semiconductor layers. The thickness of the semiconductor layer is less than 1500 Å,...
7545042 Structure combining an IC integrated substrate and a carrier, and method of manufacturing such structure  
The present invention provides a structure combining an IC integrated substrate and a carrier, which comprises a carrier and an IC integrated substrate formed on the carrier. The interface between...
7545039 Structure for reducing stress for vias and fabricating method thereof  
A structure for reducing stress for vias and a fabricating method thereof are provided. One or more wires or vias in the thickness direction are enframed with the use of a stress block in a lattice...
7544986 System including integrated circuit structures formed in a silicone ladder polymer layer  
A method of forming integrated circuit structures, such as capacitors and conductive plugs, within contact openings formed in a photosensitive silicone ladder polymer (PVSQ) is disclosed. Contact...
7538433 Semiconductor device  
A semiconductor device includes at least three or more wiring layers stacked in an interlayer insulating film on a semiconductor substrate, a seal ring provided at the outer periphery of a chip...
7538428 Semiconductor device  
A semiconductor device having macro circuit including concentrated fine interconnections and extension wiring for connecting the macro circuit and the outer circuit. The widths of the fine...
7535103 Structures and methods to enhance copper metallization  
Disclosed structures and methods inhibit atomic migration and related capacitive-resistive effects between a metallization layer and an insulator layer in a semiconductor structure. One exemplary...
7528488 Method for connecting electrodes, surface-treated wiring board and adhesive film used in the method, and electrode-connected structure  
The present invention relates to a method for connecting electrodes comprising: interposing the polyphthalide represented by the formula (I): wherein R represents a divalent aromatic...
7528487 Semiconductor device having insulating material dispersed with conductive particles which establish electrical connection by penetrating to both copper conductive layer and land of wiring board  
A semiconductor device including: a semiconductor chip including a substrate, an outer-connection electrode, and a bump, wherein the bump has a first conductive layer and a second conductive layer...
7521355 Integrated circuit insulators and related methods  
A system and method for providing low dielectric constant insulators in integrated circuits is provided. One aspect of this disclosure relates to a method for forming an integrated circuit...
7518243 Semiconductor device with multilayer interconnection structure  
A semiconductor device with a multilayer interconnection structure comprises a semiconductor substrate, a plurality of metal wiring layers provided on the semiconductor device and electrically...
7514791 High reliability multilayer circuit substrates  
A multilayer circuit substrate for multi-chip modules or hybrid circuits includes a dielectric base substrate, conductors formed on the base substrate and a vacuum deposited dielectric thin film...
7514355 Multilayer interconnection structure and method for forming the same  
A multilayer interconnection structure of the present invention includes first interconnection, second interconnection belonging to an interconnection layer different from an interconnection layer...
7511378 Enhancement of performance of a conductive wire in a multilayered substrate  
An electronic structure having wiring, and an associated method of designing the structure, for limiting a temperature gradient in the wiring. The electronic structure includes a substrate having a...
7511365 Thermal enhanced low profile package structure  
A thermal enhanced low profile package structure and a method for fabricating the same are provided. The package structure typically includes a metallization layer with an electronic component...
7508082 Semiconductor device and method of manufacturing the same  
There is provided a solution to the problem of the poor adhesion in the pad portion while inhibiting the dishing in the pad portion. An SiON film, which covers insulating areas and has an opening...
7507660 Deposition processes for tungsten-containing barrier layers  
In one embodiment, a method for forming a barrier material on a substrate is provided which includes exposing a dielectric layer on the substrate to a plasma during a preclean process, wherein the...
7504724 Semiconductor device  
A semiconductor device comprises: a plurality of first wiring lines formed in a first layer with a first wiring width and a first wiring space; a plurality of second wiring lines formed in a second...
7501705 Configuration terminal for integrated devices and method for configuring an integrated device  
A configuration terminal for integrated devices includes a first and a second portion structurally independent and connected to respective first and second terminals and it has at least one contact...
7495335 Method of reducing process steps in metal line protective structure formation  
A method of forming a protective structure on a top metal line on an interconnect structure is disclosed. The method includes providing a plate opening in the passivation layer on the top metal...
7495314 Ohmic contact on p-type GaN  
An ohmic contact in accordance with the invention includes a layer of p-type GaN-based material. A first layer of a group II-VI compound semiconductor is located adjacent to the layer of p-type...
7489037 Semiconductor device and fabrication method thereof  
A semiconductor device and a fabrication method thereof are proposed. A first dielectric layer is formed on a semiconductor substrate having at least one bond pad, wherein the first dielectric...
7488679 Interconnect structure and process of making the same  
A method of forming an interconnect structure in an inter-layer dielectric (ILD) material, the method include the steps of creating one or more via openings in the ILD material; forming a first...
7485961 Approach to avoid buckling in BPSG by using an intermediate barrier layer  
A method is disclosed for reducing the effects of buckling, also referred to as cracking or wrinkling in multilayer heterostructures. The present method involves forming a planarization layer...
7485578 Semiconductor device  
Embodiments relate to a semiconductor device and a method of fabricating semiconductor device, that may uniformly form a barrier layer in a via hole to thus prevent layers from being broken. In...
7482685 Ceramic circuit board, method for making the same, and power module  
In a ceramic circuit board 1 prepared by integrally joining a circuit layer 4 composed of a clad member including a circuit plate 2 made of an Al plate and an Al—Si brazing material layer ...
7479699 Seal ring structures with unlanded via stacks  
Techniques for an integrated circuit device are provided. The integrated circuit device includes a semiconductor substrate, an integrated circuit, a dielectric layer, and a sealing structure. The...
7476603 Printing conductive patterns using LEP  
A method of printing an electrode component is disclosed. The method can include steps of electrostatically printing a polymer onto a substrate, where at least a portion of the printing occurs...
7474001 Method for in-line monitoring of via/contact holes etch process based on test structures in semiconductor wafer manufacturing  
A method for in-line monitoring of via/contact etching process based on a test structure is described. The test structure is comprised of via/contact holes of different sizes and densities in a...
7473642 Method for fabricating conductive layer  
A method for fabricating a conductive layer is provided. First, a substrate is provided and a patterned adhesion layer is formed on the substrate. Next, a chemical plating process is performed to...
7466025 Formation of interconnect structures by removing sacrificial material with supercritical carbon dioxide  
An inter-layer dielectric structure and method of making such structure are disclosed. A composite dielectric layer comprising a porous matrix, as well as a porogen in certain variations, is formed...
7459786 Semiconductor device  
A reliable semiconductor device having a multilayer wiring structure formed of copper as a main component material, which constrains occurrence of voids caused by stress migration. In the...
7449361 Semiconductor substrate with islands of diamond and resulting devices  
Disclosed is a method of forming a substrate having islands of diamond (or other material, such as diamond-like carbon), as well as integrated circuit devices formed from such a substrate. A...
Matches 1 - 50 out of 971 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >