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6987322 |
Contact etching utilizing multi-layer hard mask
A method for forming contact holes using a multi-layer hard mask. A substrate with a device region and an alignment region having an opening therein to serve as an alignment mark is provided. A...
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6984874 |
Semiconductor device with metal fill by treatment of mobility layers including forming a refractory metal nitride using TMEDT
A recess having a height-to-width aspect ratio from about 6:1 to about 10:1 in a semiconductor structure is disclosed with a method of forming the same. In a first embodiment, a refractory metal...
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6984875 |
Semiconductor device with improved reliability and manufacturing method of the same
A semiconductor device includes an insulating layer, a conducting portion, and a modified layer. The insulating layer is formed on a semiconductor substrate. The conducting portion is formed in the...
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6984579 |
Ultra low k plasma CVD nanotube/spin-on dielectrics with improved properties for advanced nanoelectronic device fabrication
A method for forming a conductive feature in a low k dielectric layer comprising a layer of nanotubes and a low k material between the nanotubes is provided. The low k dielectric layer may be...
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6979643 |
Interlayer connections for layered electronic devices
In a method for forming interlayer connections, metal conducting paths in an overlaying layer and vias forming the deposit in one and the same operation. In an interlayer connection formed in this...
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6977438 |
Dual damascene circuit with upper wiring and interconnect line positioned in regions formed as two layers including organic polymer layer and low-permittivity layer
A dual damascene circuit has lower wiring and upper wiring positioned in regions formed as two layers including a CH-based organic polymer layer and a low-permittivity layer made of porous MSQ or...
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6974970 |
Semiconductor device
Thin films are disclosed that are suitable as dielectrics in IC's and for other similar applications. In particular, the invention concerns thin films comprising compositions obtainable by...
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6975032 |
Copper recess process with application to selective capping and electroless plating
An integrated circuit structure is disclosed that has a layer of logical and functional devices and an interconnection layer above the layer of logical and functional devices. The interconnection...
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6972492 |
Method and structure to form capacitor in copper damascene process for integrated circuit devices
A method and resulting structure of forming a metal on metal capacitor structure for an integrated circuit device, e.g., mixed signal. The method includes forming a dual damascene structure, where...
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6967398 |
Module power distribution network
A multi-layer module for packaging an electronic component comprises an uppermost electrically conductive layer for mounting the component, a plurality of electrically insulative layers, and a...
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6960829 |
Method for producing a semiconductor wafer, semiconductor chip, and intermediate semiconductor product
A semiconductor wafer is produced with an outer contact layer applied to the entire surface of an insulating layer and a rewiring layer embedded therein. At the same time, fuses are...
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6955948 |
Method of manufacturing a component built-in module
A component built-in module includes an electric insulation layer, first wiring patterns in a plurality of layers that are laminated with the electric insulation layer being interposed...
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6953996 |
Low-loss coplanar waveguides and method of fabrication
Coplanar waveguides having a deep trench between a signal line and a ground plane and methods of their fabrication are disclosed. An oxide layer is provided over a silicon substrate and a...
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6952052 |
Cu interconnects with composite barrier layers for wafer-to-wafer uniformity
A composite α-Ta/ graded tantalum nitride /TaN barrier layer is formed in Cu interconnects with a structure designed for improved wafer-to-wafer uniformity, electromigration resistance and...
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6949827 |
Semiconductor device with novel film composition
A method of depositing a thin film on a substrate in a semiconductor device using Atomic Layer Deposition (ALD) process parameters exposes the substrate to at least one adherent material in a...
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6946736 |
Electrical device including dielectric layer formed by direct patterning process
Provided is a process for lithographically patterning a material on a substrate comprising the steps of (a) depositing a radiation sensitive material on the substrate by chemical vapor deposition;...
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6946716 |
Electroplated interconnection structures on integrated circuit chips
A process is described for the fabrication of submicron interconnect structures for integrated circuit chips. Void-free and seamless conductors are obtained by electroplating Cu from baths that...
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6940170 |
Techniques for triple and quadruple damascene fabrication
The present invention provides integrated circuit fabrication methods and devices wherein triple damascene structures are formed in five consecutive dielectric layers ( 312, 314, 316, 318 and 320...
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6940171 |
Multi-layer dielectric and method of forming same
A multiple dielectric device and its method of manufacture overlaying a semiconductor material, including a substrate, an opening relative to the substrate, the opening having an aspect ratio...
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6936923 |
Method to form very a fine pitch solder bump using methods of electroplating
A new method and processing sequence is provided for the creation of interconnect bumps. A layer of passivation is deposited over a contact pad and patterned, creating an opening in the layer of...
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6936918 |
MEMS device with conductive path through substrate
A MEMS device has at least one conductive path extending from the top facing side of its substrate (having MEMS structure) to the bottom side of the noted substrate. The at least one conductive...
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6933614 |
Integrated circuit die having a copper contact and method therefor
An integrated circuit die ( 10 ) has a copper contact ( 16, 18 ), which, upon exposure to the ambient air, forms a native copper oxide. An organic material is applied to the copper contact which...
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6919635 |
High density microvia substrate with high wireability
The density of plated thru holes in a glass fiber based chip carrier is increased by off-setting holes to positions in which fibers from adjacent holes will not connect. Elongated strip zones or...
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6917112 |
Conductive semiconductor structures containing metal oxide regions
A method for forming a metal/metal oxide structure that includes forming metal oxide regions, e.g.. ruthenium oxide regions, at grain boundaries of a metal layer, e.g., platinum. Preferably, the...
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6914325 |
Power semiconductor module
A power semiconductor module has a circuit assembly body, which includes a metal base, a ceramic substrate, and a power semiconductor chip, and is combined with a package having terminals formed...
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6909188 |
Semiconductor device and manufacturing method thereof
There is disclosed a semiconductor device comprising a first wire and a pad portion thereof provided in a portion from an upper surface to an inner portion of a first insulation film provided above...
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6905967 |
Method for improving planarity of shallow trench isolation using multiple simultaneous tiling systems
In a feature layer of a semiconductor wafer, dummy tiles which overcome the tendency of dishing and erosion to occur during a CMP process are placed with various sizes and in various positions. An...
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6903459 |
High frequency semiconductor device
A high frequency (HF) semiconductor device includes a semiconductor substrate. An electroconductor layer is provided on the semiconductor substrate. A first insulator layer electrically insulates...
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6903427 |
Mask programmable read-only memory based on nF-opening mask
The present invention discloses an nF-opening-based mask-programmable read-only memory. Because its openings can be nx (n>1) wider than its address-selection lines, this memory can use less...
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6894334 |
Semiconductor integrated circuit device, process for fabricating the same, and apparatus for fabricating the same
Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by...
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6891270 |
Semiconductor device and method of manufacturing the same
A simple technique of forming a low-resistant wire is provided in place of a Damascene method. In a three-layer wire composed of a first layer metal film wire, a second layer metal film wire that...
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6891205 |
Stability in thyristor-based memory device
A semiconductor device having a thyristor-based memory device exhibits improved stability under adverse operating conditions related to temperature, noise, electrical disturbances and light. In one...
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6891272 |
Multi-path via interconnection structures and methods for manufacturing the same
A multilayered circuit component includes one or more substrates. A first surface of one of the substrates includes circuit paths and other current carrying elements. A second surface of the same...
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6891277 |
Semiconductor device alignment mark having oxidation prevention cover film
Alignment marks of a semiconductor device, formed prior to a step of applying heat treatment in an oxygen atmosphere, include an insulating film, a groove formed in the insulating film during a...
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6888244 |
Interconnect arrangement and method for fabricating an interconnect arrangement
An interconnect arrangement ( 100 ) has a first layer ( 101 ), a first layer surface ( 102 ), thereon at least two interconnects ( 104 ) having a second layer surface ( 105 ) essentially parallel...
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6888224 |
Methods and systems for fabricating electrical connections to semiconductor structures incorporating low-k dielectric materials
Low-k dielectric materials have desirable insulating characteristics for use in insulating sub micron conductors in semiconductor devices. However, certain physical and material characteristics of...
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6888246 |
Semiconductor power device with shear stress compensation
In accordance with one embodiment, a stress buffer ( 40 ) is formed between a power metal structure ( 90 ) and passivation layer ( 30 ). The stress buffer ( 40 ) reduces the effects of stress...
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6888253 |
Inexpensive wafer level MMIC chip packaging
An inexpensive package for a semiconductor chip ( 1 ) that incorporates a stress relief buffer ( 13 ) between a side of the chip and the metal carrier layer ( 2 ) to absorb thermally induced stress...
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6885110 |
Electrical circuit board and TFT array substrate and liquid crystal display device utilizing the same
TFT array substrates used for liquid crystal display panels are disclosed of which the fabrication processes are simplified and the manufacturing costs are reduced by reducing the number of masks...
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6882052 |
Plasma enhanced liner
A method and structure for forming a refractory metal liner, includes depositing a layer of refractory metal on a first conductive layer, at least half of the depositing being carried out in the...
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6882010 |
High performance three-dimensional TFT-based CMOS inverters, and computer systems utilizing such novel CMOS inverters
The invention includes three-dimensional TFT based stacked CMOS inverters. Particular inverters can have a PFET device stacked over an NFET device. The PFET device can be a...
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6879046 |
Split barrier layer including nitrogen-containing portion and oxygen-containing portion
A split barrier layer enables copper interconnect wires to be used in conjunction with low-k dielectric films by preventing the diffusion of N—H base groups into photoresists where they can...
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6876082 |
Refractory metal nitride barrier layer with gradient nitrogen concentration
Within a microelectronic fabrication and a method for fabricating the microelectronic fabrication a barrier layer is formed over a substrate. Within the method and the microelectronic fabrication...
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6876078 |
Semiconductor interconnection structure with TaN and method of forming the same
A structure includes a diffusion barrier layer pattern, a conductive layer pattern, an adhesion layer pattern, and a tantalum nitride layer pattern that are sequentially stacked over a...
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6873048 |
System and method for integrating multiple metal gates for CMOS applications
A dual-gate MOSFET with metal gates and a method for setting threshold voltage in such a MOSFET is provided. The method comprises: forming a gate oxide layer overlying first and second channel...
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6873049 |
Near hermetic power chip on board device and manufacturing method therefor
Near-hermetic performance has been reported for power semiconductor devices having a silicon carbide layer deposited on the surface at the semiconductor wafer level. The P-COB device also includes...
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6870263 |
Device interconnection
A conductor for interconnecting integrated circuit components having improved reliability. The conductor includes a liner surrounding at least three surfaces of the conductor, producing a low...
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6864521 |
Method to control silver concentration in a resistance variable memory element
A method for controlling silver doping of a chalcogenide glass in a resistance variable memory element is disclosed herein. The method includes forming a thin metal containing layer having a...
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6864581 |
Etched metal trace with reduced RF impendance resulting from the skin effect
The RF impedance of a metal trace at gigahertz frequencies is reduced by forming the metal trace to have a base region and a number of fingers that extend away from the base region. When formed to...
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6861755 |
Semiconductor device
The semiconductor device comprises an insulating film 114 formed mainly of a film of polyallyl ether resin; an interconnection structure 116 buried in the insulating film 114 , and having a...
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