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7304349 |
Power semiconductor component with increased robustness
The invention relates to a power semiconductor component with increased robustness, in which a contact layer ( 13, 14 ) applied directly to a main surface ( 7, 11 ) of the semiconductor body ( 1 )...
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7301240 |
Semiconductor device
A semiconductor device is disclosed, which includes at least two layers superposed on each other in a stacking direction above a substrate, each of the layers including an insulating film a...
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7294931 |
Method and apparatus for selective deposition
A method for selectively depositing a source material on a wafer is disclosed. In one embodiment, a wafer is having at least one recessed feature is provided. A top surface of the wafer is then...
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7291917 |
Integrated circuitry
Methods of forming contact openings, making electrical interconnections, and related integrated circuitry are described. Integrated circuitry formed through one or more of the inventive...
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7282435 |
Method of forming contact for dual liner product
A method is provided of forming a contact to a semiconductor structure. A current-conducting member is formed which extends horizontally over a first portion of a semiconductor device region but...
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7276801 |
Designs and methods for conductive bumps
Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer...
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7274091 |
Semiconductor device and method of manufacturing a semiconductor device
There is provided a semiconductor device including, a bed, a brazing filler metal formed on a first surface of the bed, a barrier metal film formed on a first surface of the brazing filler metal, a...
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7274103 |
Semiconductor device and manufacturing method thereof
In a semiconductor module connecting a semiconductor element and a passive element to a printed board, each of connection portions between the semiconductor element and the printed board and...
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7262500 |
Interconnection structure
In a metal film production apparatus, a copper plate member is etched with a Cl 2 gas plasma within a chamber to form a precursor comprising a Cu component and a Cl 2 gas; and the temperatures of...
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7262133 |
Enhancement of copper line reliability using thin ALD tan film to cap the copper line
A method for depositing a cap layer over a metal-containing interconnect is provided. In one aspect, the cap layer is formed by introducing a pulse of a metal-containing compound followed by a...
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7259461 |
Semiconductor device having improved contact hole structure and method for fabricating the same
A contact hole fabrication method for semiconductor device includes forming a dielectric layer on a semiconductor substrate, forming an antireflective layer on the dielectric layer, forming an...
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7259462 |
Interconnect dielectric tuning
An improvement to a method of forming an integrated circuit. An etch stop layer is formed to overlie the front end processing layers of the integrated circuit. Support structures are formed that...
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7256501 |
Semiconductor device and manufacturing method of the same
In a semiconductor device having a package structure in which lead terminals connected to electrodes on both of the upper and lower surfaces of a semiconductor chip are exposed from both of the...
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7256467 |
Materials and methods for forming hybrid organic-inorganic anti-stiction materials for micro-electromechanical systems
A micro-electromechanical device is formed on a substrate. The device has sliding, abrading or impacting surfaces. At least one of these surfaces is covered with an anti-stiction material. The...
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7253472 |
Method of fabricating semiconductor device employing selectivity poly deposition
A method for fabricating a semiconductor device employing a selectivity poly deposition is disclosed. The disclosed method comprises depositing selectivity poly on a gate poly and source/drain...
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7253514 |
Self-supporting connecting element for a semiconductor chip
A connecting element for electrically connecting a semiconductor chip and a superordinate circuit board includes an elastic metal strip that is bent forming two metal limbs with flattened limb...
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7247939 |
Metal filled semiconductor features with improved structural stability
A method for forming a metal filled semiconductor feature with improved structural stability including a semiconductor wafer having an anisotropically etched opening formed through a plurality of...
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7242098 |
Barrier film integrity on porous low k dielectrics by application of a hydrocarbon plasma treatment
A method for treating a dielectric material using hydrocarbon plasma is described, which allows for thinner films of barrier material to be used to form a robust barrier.
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7242097 |
Electromigration barrier layers for solder joints
A microelectronic package is disclosed including a microelectronic device, a substrate, and a signaling path coupling the microelectronic device with the substrate. The signaling path includes a...
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7239019 |
Selectively converted inter-layer dielectric
An inter-layer dielectric structure and method of making such structure are disclosed. A composite dielectric layer, initially comprising a porous matrix and a porogen, is formed. Subsequent to...
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7235882 |
Semiconductor device having a wiring layer of damascene structure and method for manufacturing the same
In a semiconductor device, a wiring pattern groove is formed in a surface portion of a silicon oxide film provided above a semiconductor substrate. A wiring layer is buried into the wiring pattern...
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7235310 |
Hillock-free aluminum layer and method of forming the same
A hillock-free conductive layer comprising at least two aluminum (Al) layers formed on a substrate, wherein said at least two Al layers comprise a barrier Al layer formed on the substrate, and a...
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7233069 |
Interconnection substrate and fabrication method thereof
An interconnection substrate includes: an interconnection layer region where at least a first conductor layer and a second conductor layer are vertically stacked in that order on a substrate, with...
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7233070 |
Semiconductor device having no cracks in one or more layers underlying a metal line layer and method of manufacturing the same
A semiconductor device and a method of manufacturing the same which yields high reliability and a high manufacturing yield. The semiconductor device includes a metal line layer having a plurality...
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7224060 |
Integrated circuit with protective moat
A method of manufacturing an integrated circuit provides a substrate having a semiconductor device, and includes forming an intermetal dielectric layer over the substrate and the semiconductor...
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7224064 |
Semiconductor device having conductive interconnections and porous and nonporous insulating portions
A semiconductor device and manufacturing method, wherein the semiconductor device has a semiconductor substrate on which a plurality of elements constituting a logic type device have been formed; a...
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7224054 |
Semiconductor device and system having semiconductor device mounted thereon
A ball grid array packaged semiconductor device mounted on a mounting board and including pads formed within a package and are connected to signal lines of a bare chip by bonding wires. There are...
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7215000 |
Selectively encased surface metal structures in a semiconductor device
The present invention provides, in one embodiment, An integrated circuit device ( 100 ). The integrated circuit device ( 100 ) comprises a circuit feature ( 105 ) located over a semiconductor...
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7214576 |
Manufacturing method of semiconductor device
A manufacturing method of a semiconductor device disclosed herein comprises: forming a first protrusion; forming a second protrusion which is higher than the first protrusion; forming a first...
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7208829 |
Semiconductor component
A semiconductor component that is able to be produced simply, quickly, and yet reliably and that usable for power applications, and including a semiconductor chip, a lower, first main electrode...
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7205674 |
Semiconductor package with build-up layers formed on chip and fabrication method of the semiconductor package
A semiconductor package with build-up layers formed on a chip and a fabrication method of the semiconductor package are provided. A chip with a plurality of conductive bumps formed on bond pads...
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7202566 |
Crossed power strapped layout for full CMOS circuit design
An integrated circuit device and method thereof includes a substrate and a plurality of microelectronic devices. Each of the microelectronics devices includes a patterned feature located over the...
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7202567 |
Semiconductor device and manufacturing method for the same
A lower interconnection is provided on a semiconductor substrate. A MIM capacitive element is provided on a first interlayer insulation film in which the lower interconnection is buried, and...
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7199474 |
Damascene structure with integral etch stop layer
This invention relates to a semiconductor structure for dual damascene processing and includes upper and lower low k dielectric layers formed in a stack when the upper surface of the lower layer...
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7199472 |
Semiconductor device
In a semiconductor device having the upmost wiring layer comprised of aluminum and the wiring layer immediately below it comprised of copper, the upmost wiring layer is made thicker than the wiring...
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7187059 |
Compressive SiGe <110> growth and structure of MOSFET devices
A structure for conducting carriers and method for forming is described incorporating a single crystal substrate of Si or SiGe having an upper surface in the <110> and a psuedomorphic or...
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7183656 |
Bilayer aluminum last metal for interconnects and wirebond pads
A method for connecting a microelectronic device to a wirebond comprises providing a substrate having a microelectronic circuit therein and forming a wiring layer over the substrate. The wiring...
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7180187 |
Interlayer connector for preventing delamination of semiconductor device
An interlayer connector for preventing delamination of semiconductor layers, and methods of forming the connector are disclosed. The connector includes a first connector head in a first distal...
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7180180 |
Stacked device underfill and a method of fabrication
Numerous embodiments of a stacked device underfill and a method of formation are disclosed. In one embodiment, a method of forming stacked semiconductor device with an underfill comprises forming...
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7180188 |
Contact structure of semiconductor devices and method of fabricating the same
A contact structure includes a lower conductive pattern disposed on a predetermined region of a semiconductor substrate. The lower conductive layer has a concave region at a predetermined region of...
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7176571 |
Nitride barrier layer to prevent metal (Cu) leakage issue in a dual damascene structure
A method for forming a composite barrier layer that also functions as an etch stop in a damascene process is disclosed. A SiC layer is deposited on a substrate in a CVD process chamber followed by...
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7173339 |
Semiconductor device having a substrate an undoped silicon oxide structure and an overlaying doped silicon oxide structure with a sidewall terminating at the undoped silicon oxide structure
An etchant including C 2 H x F y , where x is an integer from two to five, inclusive, where y is an integer from one to four, inclusive, and where x plus y equals six, etches doped silicon dioxide...
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7164208 |
Semiconductor device and method for manufacturing the same
There is provided a semiconductor device in which the junction strength of land portions and external terminals is increased, the disconnection of the external terminal is surely prevented, and the...
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7157755 |
Polymer sacrificial light absorbing structure and method
Method and structure for optimizing dual damascene patterning with polymeric dielectric materials are disclosed. Certain embodiments of the invention comprise polymeric sacrificial light absorbing...
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7158549 |
Support structure for an optical device
An optical subassembly includes a substrate, a heat spreader, and a submount. The submount has a submount mounting surface and a component mounting surface with either the submount mounting surface...
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7154177 |
Semiconductor device with edge structure
A semiconductor device has an edge termination region ( 15 ) having a plurality of trenches ( 17 ). Conductive material ( 20 ) and insulating material ( 19 ) is formed at the trenches, and surface...
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7151052 |
Multiple etch-stop layer deposition scheme and materials
Described are methods and structures for mitigating the effects of mechanical stresses placed on the layers of semiconductor devices, and specifically disclosed are methods and structures for...
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7151314 |
Semiconductor device with superimposed poly-silicon plugs
A semiconductor device includes a first insulating layer; a first poly-silicon plug formed in the first insulating layer; a second insulating layer, formed on the first insulating layer; and a...
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7148570 |
Low resistivity titanium silicide on heavily doped semiconductor
Low resistivity, C54-phase TiSi 2 is formed in narrow lines on heavily doped polysilicon by depositing a bi-layer silicon film. A thin, undoped amorphous layer is deposited on top of a heavily...
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7145238 |
Semiconductor package and substrate having multi-level vias
A semiconductor package and substrate having multi-level plated vias provide a high density blind via solution at low incremental cost. Via are half-plated atop a circuit pattern and then a second...
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