|
Match
|
Document |
Document Title |
|
|
7476603 |
Printing conductive patterns using LEP
A method of printing an electrode component is disclosed. The method can include steps of electrostatically printing a polymer onto a substrate, where at least a portion of the printing occurs...
|
|
|
7474001 |
Method for in-line monitoring of via/contact holes etch process based on test structures in semiconductor wafer manufacturing
A method for in-line monitoring of via/contact etching process based on a test structure is described. The test structure is comprised of via/contact holes of different sizes and densities in a...
|
|
|
7473642 |
Method for fabricating conductive layer
A method for fabricating a conductive layer is provided. First, a substrate is provided and a patterned adhesion layer is formed on the substrate. Next, a chemical plating process is performed to...
|
|
|
7466025 |
Formation of interconnect structures by removing sacrificial material with supercritical carbon dioxide
An inter-layer dielectric structure and method of making such structure are disclosed. A composite dielectric layer comprising a porous matrix, as well as a porogen in certain variations, is formed...
|
|
|
7459786 |
Semiconductor device
A reliable semiconductor device having a multilayer wiring structure formed of copper as a main component material, which constrains occurrence of voids caused by stress migration. In the...
|
|
|
7449361 |
Semiconductor substrate with islands of diamond and resulting devices
Disclosed is a method of forming a substrate having islands of diamond (or other material, such as diamond-like carbon), as well as integrated circuit devices formed from such a substrate. A...
|
|
|
7443019 |
Semiconductor device with conductor tracks between semiconductor chip and circuit carrier and method for producing the same
The invention relates to a semiconductor device with conductor tracks between a semiconductor chip and a circuit carrier, and to a method for producing the same. The conductor tracks extend from...
|
|
|
7443032 |
Memory device with chemical vapor deposition of titanium for titanium silicide contacts
A titanium layer is formed on a substrate with chemical vapor deposition (CVD). First, a seed layer is formed on the substrate by combining a first precursor with a reducing agent by CVD. Then, the...
|
|
|
7442961 |
Image display device
The present invention provides an image display device, by which it is possible to prevent dielectric breakdown between a bottom electrode and a top electrode (top electrode bus line), which make...
|
|
|
7439624 |
Enhanced mechanical strength via contacts
The present invention provides an enhanced interconnect structure with improved reliability. The inventive interconnect structure has enhanced mechanical strength of via contacts provided by...
|
|
|
7439623 |
Semiconductor device having via connecting between interconnects
A first insulating film is provided between a lower interconnect and an upper interconnect. The lower interconnect and the upper interconnect are connected to each other by way of a via formed in...
|
|
|
7432594 |
Semiconductor chip, electrically connections therefor
A semiconductor device has a semiconductor chip including first and second surfaces opposed to each other in a thickness direction of the semiconductor chip, wherein the first and second surfaces...
|
|
|
7432584 |
Leadframe for use in a semiconductor package
A leadframe comprises a die mounting area, a plurality of lead fingers and a metal deposit having a negative electrochemical potential with respect to a standard H 2 half cell. A semiconductor...
|
|
|
7423332 |
Vertical laminated electrical switch circuit
A vertical laminated electrical switch circuit includes a first, second, and third ceramic substrate positioned in juxtaposed relationship relative to each other. The circuit also includes a first...
|
|
|
7423343 |
Wiring board, manufacturing method thereof, semiconductor device and manufacturing method thereof
The invention provides a wiring board having a small-scale and high-performance functional circuit while realizing a multi-layer wiring with a small number of steps. In addition, the invention...
|
|
|
7420276 |
Post passivation structure for semiconductor chip or wafer
The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor wafer, post-passivation. The thick,...
|
|
|
7420211 |
Wiring line and manufacture process thereof, and semiconductor device and manufacturing process thereof
To provide a technique for manufacturing a wiring line having a low resistance and a high heat resistance so as to make an active matrix type display device larger and finer. The wiring line is...
|
|
|
7417316 |
Wired circuit forming board, wired circuit board, and thin metal layer forming method
A wired circuit forming board that can provide improved adhesion between an insulating layer and a conductive pattern and can also prevent delamination in a thin metal layer, a wired circuit board...
|
|
|
7417264 |
Top-emitting nitride-based light emitting device and method of manufacturing the same
Provided are a top-emitting N-based light emitting device and a method of manufacturing the same. The device includes a substrate, an n-type clad layer, an active layer, a p-type clad layer, and a...
|
|
|
7414275 |
Multi-level interconnections for an integrated circuit chip
Multilevel metallization layouts for an integrated circuit chip including transistors having first, second and third elements to which metallization layouts connect. The layouts minimize current...
|
|
|
7411301 |
Semiconductor integrated circuit device
In a semiconductor integrated circuit device having plural layers of buried wirings, it is intended to prevent the occurrence of a discontinuity caused by stress migration at an interface between a...
|
|
|
7411299 |
Passivation film of semiconductor device
Disclosed are a method of manufacturing a semiconductor device and a structure of a semiconductor device. A method of forming a passivation film of a semiconductor device comprises the steps of...
|
|
|
7405480 |
Elimination of thermal deformation in electronic structures
A flexible electronic display device is provided comprising a substrate; an imaging layer zone; a transparent superstrate; and a thermal control layer. The device is able to resist thermal...
|
|
|
7405419 |
Unidirectionally conductive materials for interconnection
A method of forming and a device including an interconnect structure having a unidirectional electrical conductive material is described. The unidirectional conductive material may overlie...
|
|
|
7402883 |
Back end of the line structures with liner and noble metal layer
A back end of the line (BEOL) structure of a semiconductor device is presented. In one embodiment, the structure may include a first liner layer disposed on an intermediate interconnect structure,...
|
|
|
7400041 |
Compliant multi-composition interconnects
A compliant interconnect with two or more layers of metal of two or more compositions with internal stresses is described herein.
|
|
|
7397125 |
Semiconductor device with bonding pad support structure
A semiconductor device having bonding pads on a semiconductor substrate includes: an upper copper layer that is formed on the lower surface of the bonding pads with a barrier metal interposed and...
|
|
|
7397122 |
Metal wiring for semiconductor device and method for forming the same
A metal wiring for a semiconductor device and a method for forming the same are provided. The metal wiring includes a first insulating layer and a second insulating layer; an interlayer insulating...
|
|
|
7382051 |
Semiconductor device with reduced contact resistance
A semiconductor device that includes an electrode of one material and a conductive material of lower resistivity formed over the electrode and a process for fabricating the semiconductor device.
|
|
|
7382049 |
Chip package and bump connecting structure thereof
A chip package includes a chip, a carrier, and at least a bump connecting structure for connecting the chip to the carrier. The bump connecting structure includes a first metal bump disposed on a...
|
|
|
7382037 |
Semiconductor device with a peeling prevention layer
The invention is directed to improvement of reliability of a semiconductor device having penetrating electrodes by preventing a protection film and an insulation film peeling. A peeling prevention...
|
|
|
7371679 |
Semiconductor device with a metal line and method of forming the same
A method of forming a metal line in a semiconductor device including forming an inter-metal dielectric (IMD) layer on the semiconductor substrate including the predetermined pattern, planarizing...
|
|
|
7372153 |
Integrated circuit package bond pad having plurality of conductive members
An integrated circuit package bond pad includes an insulating layer and an electrode located over the insulating layer. The electrode has a first surface configured to be bonded to external...
|
|
|
7368392 |
Method of fabricating a gate structure of a field effect transistor having a metal-containing gate electrode
A method of etching metals and/or metal-containing compounds using a plasma comprising a bromine-containing gas. In one embodiment, the method is used during fabrication of a gate structure of a...
|
|
|
7361991 |
Closed air gap interconnect structure
A closed air gap interconnect structure is described. The structure includes discrete regions of a permanent support dielectric under the interconnect lines so that the lines are substantially...
|
|
|
7362491 |
Heated glass panels and methods for making electrical contact with electro-conductive films
A heated glass panel assembly according to one embodiment of the invention may include a substrate having an electro-conductive film provided thereon. A conductor is positioned in contact with the...
|
|
|
7358618 |
Semiconductor device and manufacturing method thereof
A semiconductor device having a semiconductor substrate, at least one of a protruding electrode and wiring formed on one surface of the semiconductor substrate, and a first resin film formed on...
|
|
|
7352064 |
Multiple layer resist scheme implementing etch recipe particular to each layer
Methods of forming a metal line and/or via critical dimension (CD) in a single or dual damascene process on a semiconductor substrate, and the resist scheme implemented, are disclosed. The method...
|
|
|
7348669 |
Bump structure of semiconductor device and method of manufacturing the same
In connection with a bump of a semiconductor device and a manufacturing method thereof, a groove is formed in a bump pad region of a semiconductor substrate. An under bump metal layer is then...
|
|
|
7332433 |
Methods of modulating the work functions of film layers
Methods for fabricating two metal gate stacks with varying work functions for complementary metal oxide semiconductor (CMOS) devices are provided A first metal layer may be deposited onto a gate...
|
|
|
7323781 |
Semiconductor device and manufacturing method thereof
The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring...
|
|
|
7321166 |
Wiring board having connecting wiring between electrode plane and connecting pad
It is to provide a wiring board for a semiconductor integrated circuit package, which exhibits an excellent signal property and a high effect for decreasing the switching noise at the time of...
|
|
|
7321171 |
Semiconductor integrated circuit device
A barrier layer and a copper film are successively formed on a silicon oxide film including a groove for wiring in the silicon oxide film and a silicon nitride film, both formed on a semiconductor...
|
|
|
7319271 |
Semiconductor device
Disclosed herein is a semiconductor device having a multi-layer wiring structure includes a plurality of wiring layers laminated on a substrate, the wiring layers each including a buried wiring and...
|
|
|
7319270 |
Multi-layer electrode and method of forming the same
An interconnect includes an opening formed in a dielectric layer. A conductive barrier is deposited in the opening, over which a first conductive layer is deposited. A conductive oxide is deposited...
|
|
|
7317252 |
Ohmic contact configuration
A contact configuration has an ohmic contact between a metalization layer and a semiconductor body of monocrystalline semiconductor material. An amorphous semiconductor layer is formed between the...
|
|
|
7315083 |
Circuit device and manufacturing method thereof
A circuit device suitable for connecting a plurality of laminated wiring layers to each other through an insulating layer, and a manufacturing method thereof are provided. According to a hybrid...
|
|
|
7312486 |
Stripe board dummy metal for reducing coupling capacitance
Dishing is known to be a problem after CMP of dielectric layers in which the distribution of embedded metal is non-uniform. This problem has been solved by populating those areas where the density...
|
|
|
7307342 |
Interconnection structure of integrated circuit chip
An interconnection structure includes an integrated circuit (IC) chip having internal circuitry and a terminal to electrically connect the internal circuitry to an external circuit, a passivation...
|
|
|
7304388 |
Method and apparatus for an improved air gap interconnect structure
In one embodiment, an apparatus comprises a first layer having at least one interconnect formed in an interlayer dielectric (ILD), a second layer formed over the first layer having a second at...
|