Matches 551 - 600 out of 978 < 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 >
Match Document Document Title
6130481 Semiconductor integrated circuit interconnection structures and method of making the interconnection structures  
A semiconductor integrated circuit structure includes a semiconductor substrate; an electronic element disposed in the substrate; a first electrically insulating layer disposed on the substrate and...
6127731 Capped solder bumps which form an interconnection with a tailored reflow melting point  
The melting point of the solder forming a controlled collapse chip connection is tailored by forming a thin metal cap of a metal such as palladium or silver on a solder bump. When the solder bump...
6127734 Semiconductor device comprising a contact hole of varying width thru multiple insulating layers  
An opening having a diameter smaller than a minimum possible dimension formable by photolithography is formed in an insulating layer on an interlayer insulating layer covering an MOS transistor. An...
6127730 Composite metal films for severe topology interconnects  
A process for forming a smooth conformal refractory metal film on an insulating layer having a via formed therein. This process provides extremely good planarity and step coverage when used to form...
6121684 Integrated butt contact having a protective spacer  
The present invention provides a structure and method of forming a butting contact having protective spacers 50A that prevent shorting between a second polysilicon layer 60 and the substrate in a...
6100205 Intermetal dielectric layer formation with low dielectric constant using high density plasma chemical vapor deposition process  
A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the deposition of dielectric layers using high density plasma chemical...
6100591 Semiconductor device and method of fabricating the same  
There is provided a semiconductor device including a substrate, a first insulating film formed on the substrate, a first electrically conductive layer formed on the first insulating film, a...
6097090 High integrity vias  
Vias are formed by depositing a hard dielectric mask layer on the upper surface of a lower metal feature and forming sidewall spacers on the side surfaces of the metal feature and mask layer....
6093966 Semiconductor device with a copper barrier layer and formation thereof  
A method of forming a semiconductor device by first providing a substrate in a processing chamber. The substrate has an insulating layer and an opening in the insulating layer. A copper barrier...
6091115 Semiconductor device including a crystalline silicon film  
A semiconductor device having a CMOS structure comprising N-channel type and P-channel type insulated gate semiconductor devices combined in a complementary manner, wherein the threshold voltage of...
6091148 Electrical connection for a semiconductor structure  
The present invention relates to high aspect-ratio electrical connections, wiring trenches, and methods of forming the same in semiconductor devices. In particular, the present invention relates to...
6087724 HSQ with high plasma etching resistance surface for borderless vias  
HSQ is employed for gap filling patterned metal layers. The surface of the deposited HSQ gap fill layer is modified to decrease its plasma etching rate. Embodiments include modifying the HSQ...
6087711 Integrated circuit metallization with superconductor BEOL wiring  
The present invention discloses an integrated circuit that is wired with a high-temperature superconductive material that is superconductive at temperatures of about 70° K and above, and methods...
6083822 Fabrication process for copper structures  
A process for creating a dual damascene opening, in a composite insulator layer, to be used to accommodate a dual damascene copper structure, has been developed. The process features the use of a...
6081033 Interconnections for semiconductor circuits  
Interconnections carrying the greatest currents within a semiconductor circuit are formed by an interconnect having at least one and commonly two or more ribs extending generally orthogonally from...
6077772 Methods of forming metal interconnections including thermally treated barrier layers  
A method of forming a metal interconnection includes the steps of forming a first conductive layer on a substrate, and forming an insulating layer on the first conductive layer and on the...
6078105 Method for manufacturing semiconductor device using spin on glass layer  
In a method for manufacturing a semiconductor device, a dummy pattern layer is formed on a layer which is located below an insulating layer on which a spin on glass (SOG) layer is formed. The...
6075292 Semiconductor device and method of manufacturing the same in which degradation due to plasma can be prevented  
In a semiconductor device, a metal oxide semiconductor (MOS) transistor is formed on a semiconductor substrate to have a gate electrode which is formed on a gate oxide film. The first insulating...
6075264 Structure of a ferroelectric memory cell and method of fabricating it  
A method of fabricating A ferroelectric memory cell composed of an MOS transistor and A ferroelectric capacitor formed over A semiconductor substrate, comprises the steps of forming A contact hole...
6072225 Microelectronic devices having interconnects with planarized spun-on glass regions  
An interconnect in a microelectronic device is formed by forming a first mesa on a substrate. A first insulation layer is then formed on the substrate, the first insulation layer covering the first...
6066891 Electrode for semiconductor device including an alloy wiring layer for reducing defects in an aluminum layer and method for manufacturing the same  
The purpose of the present invention is to obtain an electrode wiring structure for semiconductor devices that can suppress the occurrence of Al voids inside aluminum alloy wiring without regard to...
6064094 Over-voltage protection system for integrated circuits using the bonding pads and passivation layer  
A protection system for integrated circuits which prevents inadvertent damage caused by over-voltage power surges by extending the passivation layer of an integrated circuit over the bonding pads...
6061251 Lead-frame based vertical interconnect package  
A vertical interconnect package for electronic components and a method to manufacture same. The invention provides a tripartite lead frame-based Vertical Interconnect Package (VIP) which provides...
6054771 Interconnection system in a semiconductor device  
An interconnection system in a semiconductor device comprises a Ti 2 N film having a lower resistivity and a higher thermal stability at a higher temperature compared to a TiN film. The Ti 2 N...
6054768 Metal fill by treatment of mobility layers  
A recess having a height-to-width aspect ratio from about 6:1 to about 10:1 in a semiconductor structure is taught with a method of forming the same. In a first embodiment, a refractory metal layer...
6051885 Semiconductor device having a conductor with a wedge shaped depression  
A highly integrated semiconductor device is made using a high precision manufacturing process having a comparatively small number of process steps. The device is substantially free of misalignment...
6051879 Electrical interconnection for attachment to a substrate  
The present invention is An electrical interconnection on a substrate and a method for forming an electrical interconnection on a substrate. The electrical interconnection in the present invention...
6049132 Multiple metallization structure for a reflection type liquid crystal display  
In a semiconductor chip for Si chip based liquid crystal having insulating films and interconnection layers formed on a semiconductor substrate, a thin interconnection layer made of TiN/Ti having...
6049130 Semiconductor device using gold bumps and copper leads as bonding elements  
A semiconductor device comprises a semiconductor chip, an Au bump formed on the semiconductor chip, and Cu lead bonded to the Au bump through a bonding part. The Cu lead has a Cu core and a plated...
6040627 Semiconductor device and method of manufacturing semiconductor device  
A semiconductor device is formed with interconnections having reduced electric resistance. The semiconductor device comprises an upper wiring formed on an insulating film with a barrier metal...
6037668 Integrated circuit having a support structure  
In one embodiment of the invention, conductive support structures (112) are formed within an interlevel dielectric layer. The conductive support structures (112) lie within the bond pad region...
6034431 Electronic integrated circuit with optical inputs and outputs  
A method for designing an integrated circuit having optical inputs and outputs includes the step of selecting an integrated circuit design which includes at least one circuit cell design for...
6028359 Integrated circuit having amorphous silicide layer in contacts and vias and method of manufacture therefor  
An integrated circuit, a contact and a method of manufacture therefor. The integrated circuit has a silicon substrate with a recess formed therein that provides an environment within which the...
6025242 Fabrication of semiconductor device having shallow junctions including an insulating spacer by thermal oxidation creating taper-shaped isolation  
A semiconductor device having shallow junctions is provided by providing a semiconductor substrate having source and drain regions and polysilicon gate regions; depositing selective silicon on the...
6025645 Semiconductor device and method of manufacturing the same  
After forming the first contact embedded in the first insulating film, a wire is formed on the first contact and a side wall made of an insulative substance is formed on a side surface of the wire....
6020639 Semiconductor wafer with removed CVD copper  
A method of using diluted nitric acid and an edge bead removal tool to remove copper from the perimeter of a semiconductor wafer is provided. In one embodiment, sensitive areas of the wafer are...
6016011 Method and apparatus for a dual-inlaid damascene contact to sensor  
A dual-inlaid damascene contact having a polished surface for directly communicating an electrically conductive layer to a semiconductor layer. A dielectric layer is formed on the electrically...
6016010 Voidless metallization on titanium aluminide in an interconnect  
Disclosed is a method for in situ formation of titanium aluminide. The disclosed method is directed to overcoming voiding problems which result in conventional titanium and aluminum metal...
6013952 Structure and method for measuring interface resistance in multiple interface contacts and via structures in semiconductor devices  
A structure and method is shown for measuring a plug and interface resistance values of an inter-layer contact structure in a semiconductor device. An inter-layer contact plug interconnects two...
6013951 Semiconductor device having an improved lead connection structure and manufacturing method thereof  
A first polycide lead, which is formed on a silicon substrate, consists of a first doped polysilicon layer and a first tungsten silicide layer that is formed on the first doped polysilicon layer....
6005291 Semiconductor device and process for production thereof  
A semiconductor device comprising an insulating film at least partially containing a fluorine-containing film, formed above a semiconductor substrate, and a titanium nitride film formed on the...
6002176 Differential copper deposition on integrated circuit surfaces  
A method for selectively applying CVD copper to metallic surfaces, that are co-located with non-metallic surfaces, is provided. The method prepares both the metal and non-metallic surfaces with a...
5998844 Semiconductor constructions comprising electrically conductive plugs having monocrystalline and polycrystalline silicon  
A method of forming a field effect transistor relative to a monocrystalline silicon substrate, where the transistor has an elevated source and an elevated drain, includes: a) providing a transistor...
5994767 Leadframe for integrated circuit package and method of manufacturing the same  
A leadframe for an IC package and a method of manufacturing the same are provided. The leadframe can be manufactured in such a manner as to provide suitable bondability, molding compound...
5994221 Method of fabricating aluminum-indium (or thallium) vias for ULSI metallization and interconnects  
The present invention provides a method of forming an alloy interconnect in an integrated circuit having a dielectric layer with an opening formed therein. In an advantageous embodiment, the method...
5990555 Electronic circuit device with multi-layer wiring  
An electronic circuit having: a substrate with an upper surface; a lower level wiring made of conductive material and disposed on the substrate; an insulating cover film covering the surface of the...
5990556 Stacked thin film assembly  
A stacked film assembly for use as wiring in a semiconductor device having a bottom film (CVD-W film) 33 and a top film (Al alloy film) 12, where the surface roughness (Ra) of the bottom film is...
5977599 Formation of a metal via using a raised metal plug structure  
A process has been developed which allows contact between levels of interconnect metallization structures, to occur without the use of via holes, etched in interlevel insulator layers. The process...
5969420 Semiconductor device comprising a plurality of interconnection patterns  
On transistors P1, P2, N1 and N2 constituting an NAND gate, interconnection pattern W of metal having high melting point and aluminum interconnection patterns Al1 and Al2 are stacked. A local line...
5966294 Printed circuit board for prevention of unintentional electromagnetic interference  
There is provided a printed circuit board including (a) at least one dielectric layer, (b) at least two metal layers one of which acts as a ground layer, another one of which acts as a...
Matches 551 - 600 out of 978 < 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 >