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7432559 Silicide formation on SiGe  
A semiconductor structure includes a first silicon-containing layer comprising an element selected from the group consisting essentially of carbon and germanium wherein the silicon-containing layer...
7368822 Copper metalized ohmic contact electrode of compound device  
The present invention provides an ohmic contact for a copper metallization whose heat diffusion is improved and cost is reduced. Therein, the ohmic contact is formed through a depositing and an...
7276794 Junction-isolated vias  
A process for forming a junction-isolated, electrically conductive via in a silicon substrate and a conductive apparatus to carry electrical signal from one side of a silicon wafer to the other...
7235469 Semiconductor device and method for manufacturing the same  
A semiconductor device suitable for the miniaturization and comprising properly controlled Si/SiGe gate electrode comprises an insulator formed on a semiconductor substrate, a first gate electrode...
6902258 LDMOS and CMOS integrated circuit and method of making  
An integrated circuit (IC) is formed on a substrate. The IC has a first well having a first dopant concentration that includes a second conductivity low-voltage transistor. The IC also has a second...
6784550 Thermal processing of metal alloys for an improved CMP process in integrated circuit fabrication  
A thermal processing method is described which improves integrated circuit metal polishing and increases conductivity following polish. A method of fabricating a metal layer in an integrated...
6767842 Implementation of Si-Ge HBT with CMOS process  
A semiconductor device wherein Si—Ge is the base of a bipolar transistor and a Silicon layer is the emitter. A method of making such a semiconductor device including steps of forming a Silicon...
6734515 Semiconductor light receiving element  
A semiconductor light receiving element having a light receiving layer ( 1 ) formed from a GaN group semiconductor, and an electrode ( 2 ) formed on one surface of the light receiving layer as a...
6657303 Integrated circuit with low solubility metal-conductor interconnect cap  
An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer formed on the semiconductor substrate. A...
6541859 Methods and structures for silver interconnections in integrated circuits  
A typical integrated-circuit fabrication requires interconnecting millions of microscopic transistors and resistors with aluminum wires. Making the aluminum wires flush, or coplanar, with...
6525425 Copper interconnects with improved electromigration resistance and low resistivity  
Copper interconnects are formed by depositing substantially pure copper into the lower portion of an interconnect opening. The upper portion of the interconnect opening is then filled with doped...
6514395 Nanostructure-based high energy capacity material  
A nanostructure based material is capable of accepting-and reacting with an alkali metal such as lithium. The material exhibits a reversible capacity ranging from at least approximately 900...
6400008 Surface mount ic using silicon vias in an area array format or same size as die array  
A die incorporating vertical conductors, or vias, extending from active and passive devices on the active die side to the back side thereof. The vias are preferably formed in the die material...
6326664 Transistor with ultra shallow tip and method of fabrication  
A novel transistor with a low resistance ultra shallow tip region and its method of fabrication. The novel transistor of the present invention has a source/drain extension or tip comprising an...
6100176 Methods and structures for gold interconnections in integrated circuits  
A typical integrated-circuit fabrication requires interconnecting millions of microscopic transistors and resistors with aluminum wires. Making the aluminum wires flush, or coplanar, with...
6066876 Integrated circuit arrangement having at least one MOS transistor manufactured by use of a planar transistor layout  
An integrated circuit arrangement contains an MOS transistor surrounded by an insulation structure, the source and drain thereof being arranged laterally and in different depths. A channel thereof...
6030894 Method for manufacturing a semiconductor device having contact plug made of Si/SiGe/Si  
On a main surface of a silicon substrate of one conductivity type, a diffusion layer of the opposite conductivity type is formed, and the main surface of the silicon substrate is covered by an...
5864149 Staggered thin film transistor with transparent electrodes and an improved ohmic contact structure  
A multi-layer structure of source/drain electrodes and an amorphous silicon layer in a forward staggered thin film transistor. Source/drain electrodes are selectively provided on an insulator. Each...
5852327 Semiconductor device  
In a semiconductor substrate of a semiconductor device, a plural impurity layers of the same conductivity type as the substrate are formed. An impurity region of an opposite conductivity type...
5825052 Semiconductor light emmitting device  
A semiconductor light emitting device comprising: a substrate; and a gallium nitride type compound semiconductor layers provided on the substrate, the semiconductor layers including at least an...
5804846 Process for forming a self-aligned raised source/drain MOS device and device therefrom  
The present invention is directed to a process for forming a self-aligned raised source/drain MOS device comprising a planarized metal layer, preferably tungsten, overlying a source, a drain, and a...
5801444 Multilevel electronic structures containing copper layer and copper-semiconductor layers  
A low temperature annealed Cu silicide or germanide layer on the surface of a single crystalline semiconductor substrate of Si or Ge is used in interconnection metallization for integrated...
5777388 Semiconductor device of the type sealed in glass having a silver-copper bonding layer between slugs and connection conductors  
The invention relates to a semiconductor device of the type sealed in glass, comprising a semiconductor body having a pn-junction between opposing faces which are connected to slugs of a transition...
5653019 Repairable chip bonding/interconnect process  
A repairable, chip-to-board interconnect process which addresses cost and testability issues in the multi-chip modules. This process can be carried out using a chip-on-sacrificial-substrate...
5563448 Ohmic contact structure of a highly integrated semiconductor device having two resistance control layers formed between a metal electrode and the substrate  
An ohmic contact structure for connection of a metal electrode to a highly integrated semiconductor device and a method for making the same. A contact hole is selectively formed in an insulating...
5481137 Semiconductor device with improved immunity to contact and conductor defects  
In a semiconductor device, an impurity diffused layer serving as an active region is formed in a predetermined region of the surface of a semiconductor substrate of silicon, an underlayer...
5382808 Metal boride ohmic contact on diamond and method for making same  
An ohmic contact includes a metal boride layer on a semiconducting diamond layer. The metal boride preferably includes boron and a transition metal and, more preferably, a refractory metal. Heating...
5336903 Selective deposition of doped silicon-germanium alloy on semiconductor substrate, and resulting structures  
Doped silicon-germanium alloy is selectively deposited on a semiconductor substrate, and the semiconductor substrate is then heated to diffuse at least some of the dopant from the silicon-germanium...
5323022 Platinum ohmic contact to p-type silicon carbide  
A method and resulting ohmic contact structure between a high work function metal and a wide bandgap semiconductor for which the work function of the metal would ordinarily be insufficient to form...
5210431 Ohmic connection electrodes for p-type semiconductor diamonds  
In an ohmic contact electrode for the p-type semiconductor diamond, the electrode is formed of metals or metallic compounds containing boron on a p-type semiconductor diamond, so as to obtain a...
5192994 Au-Ge-Ni ohmic contact for Ga-Al-As compound semiconductor  
On the surface of n-type layer of Ga 1 -x Al x As (0≤x≤1) having n-type layer, Au layer is formed as a first layer, and alloying treatment is performed after Ge layer, Ni layer and Au layer...
5155560 Semiconductor index guided laser diode having both contacts on same surface  
The present invention is directed to a laser diode which is formed of a substrate of a semi-insulating material having a body of a semiconductor material on a surface thereof. The body includes a...
5126805 Junction field effect transistor with SiGe contact regions  
A junction field effect transistor, specifically a static induction transistor. Prior to metallization a thin layer of germanium is placed over the exposed silicon of the source and gate regions....
4994892 Aluminum germanium ohmic contacts to gallium arsenide  
Ohmic contacts are attached to n-type Gallium Arsenide with an alloy of Aluminum-Germanium. The contact is prepared by depositing by evaporation a sequence of 400 Angstroms of Germanium, 300...
4992847 Thin-film chip-to-substrate interconnect and methods for making same  
Integrated circuit chips are electrically connected to a silica wafer interconnection substrate. Thin film wiring is fabricated down bevelled edges of the chips. A subtractive wire fabrication...
4987562 Semiconductor layer structure having an aluminum-silicon alloy layer  
A semiconductor layer structure includes an alloy layer of aluminum and silicon formed on a silicon substrate. The concentration of silicon contained in the aluminum-silicon alloy layer is within a...
4983536 Method of fabricating junction field effect transistor  
A junction field effect transistor, specifically a static induction transistor. Prior to metallization a thin layer of germanium is placed over the exposed silicon of the source and gate regions....
4974055 Self-aligned interconnects for semiconductor devices  
A novel process is provided to fabricate interconnections (46c) in transistors (14) having self-aligned, planarized contacts (46s, 40g, 46d) in a novel, completely self-aligned configuration. The...
4965656 Semiconductor device  
This invention provides a semiconductor device having an electrode conductor layer on a semiconductor substrate through the medium of a diffusion barrier layer, comprising the diffusion barrier...
4945070 Method of making cmos with shallow source and drain junctions  
A CMOS device having shallow source and drain regions is formed in a body of single crystalline silicon having a major surface by forming in the body adjacent well regions of opposite conductivity...
4943839 Contact type image sensor  
A contact type image sensor has a transparent dielectric substrate, an upper transparent electrode, a lower electrode provided on the transparent dielectric substrate, a semiconductor thin film...
4942451 Semiconductor device having improved antireflection coating  
A semiconductor device comprises a semiconductor substrate containing silicon as a constituent element, an impurity diffused layer formed in a predetermined region of the semiconductor substrate,...
4940495 Photovoltaic device having light transmitting electrically conductive stacked films  
A light transmitting electrically conductive stacked film, useful as a light transmitting electrode, including a first light transmitting electrically conductive layer, having a first optical...
4872040 Self-aligned heterojunction transistor  
A vertical heterojunction equal area transistor and starting structure therefor is provided in which three epitaxial layers structure with wide band gap external layers and narrower band gap center...
4803539 Dopant control of metal silicide formation  
A structure and method are described for forming different metal silicide phases, using the same metallurgy and the same processing steps. A layer of metal is deposited on a silicon substrate and...
4791074 Method of manufacturing a semiconductor apparatus  
According to the present invention, a method of manufacturing a semiconductor apparatus is provided which comprises the steps of (a) depositing a boron layer on a silicon substrate, and (b)...
4743953 Random access memory cell with MIS capacitor having insulator of oxide of doped metal  
A semiconductor device such as a MIS type capacitor which including a semiconductor substrate of one conductive sign (p-type silicon substrate), a region (n-type) of conductive sign opposite to...
4733284 Semiconductor devices and laminates including phosphorus doped transparent conductive film  
A transparent conductive film formed on a transparent substrate of a thin film transistor or solar cell contains an element falling in Group III or V of the periodic table. The transparent...
4694115 Solar cell having improved front surface metallization  
A gallium arsenide solar cell is disclosed having an aluminum gallium arsenide window layer in which fine metallic contact lines extend through the aluminum gallium arsenide window to electrically...
4648175 Use of selectively deposited tungsten for contact formation and shunting metallization  
A process for using selectively deposited tungsten in the making of ohmic contacts and contact/interconnect metallization patterns. In one form the process is employed to interconnect fully formed...
Matches 1 - 50 out of 107 1 2 3 >