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7276796 Formation of oxidation-resistant seed layer for interconnect applications  
An interconnect structure of the single or dual damascene type and a method of forming the same, which substantially reduces the surface oxidation problem of plating a conductive material onto a...
6866943 Bond pad structure comprising tungsten or tungsten compound layer on top of metallization level  
A bond pad structure formed over a predetermined area of an IC substrate comprising quickly and easily removable redundancy and passivation layers upon lithography and plasma etching in a plasma...
6787908 Pad metallization over active circuitry  
Metal bond pads are formed over active circuitry in a semiconductor chip in a reliable and cost effective manner. According to an example embodiment of the present invention, a metal bond pad is...
6649995 Semiconductor device and method of manufacturing the same  
A Schottky diode that achieves a predetermined reverse-direction breakdown voltage even if a state of a surface in a vicinity of a Schottky junction interface changes due to a welding of a bonding...
6448652 Interconnect structure with a dielectric layer conforming to the perimeter of a wiring layer  
A first interlayer insulating film and an etching stopper film are sequentially formed on a semiconductor substrate with a surface area on which first wiring is formed. The etching stopper film is...
6437372 Diffusion barrier spikes for III-V structures  
A diffusion preventing barrier spike is disclosed. The spike prevents diffusion of dopants into another layer without forming a pn junction in the layer. The spikes are illustratively Al or an...
6417564 Semiconductor element with metal layer  
The invention relates to a semiconductor element which comprises a metal layer with gold and germanium. A thin covering layer of germanium oxide lies on the metal layer, protecting the subjacent...
6400026 Semiconductor device with the copper containing aluminum alloy bond pad on an active region  
In a semiconductor device, an active region is formed on a semiconductor substrate. An electrode layer is directly formed on the active region and serves as a bonding pad. The electrode layer is...
6362526 Alloy barrier layers for semiconductors  
A semiconductor barrier layer and manufacturing method therefor for copper interconnects which is a tantalum-titanium, tantalum-titanium nitride, tantalum-titanium sandwich. The tantalum in the...
6297535 Transistor having a gate dielectric which is substantially resistant to drain-side hot carrier injection  
A transistor fabrication process is provided which derives a benefit from having barrier atoms incorporated in a lateral area under a gate oxide of the transistor in close proximity to the drain....
6222267 Semiconductor device and manufacturing thereof  
A semiconductor device has: a silicon substrate; a plurality of impurity doped regions formed in a surface layer of the silicon substrate; contact layers each in contact with a surface of...
6197628 Ruthenium silicide diffusion barrier layers and methods of forming same  
A method for use in the fabrication of integrated circuits includes providing a substrate assembly having a surface. A diffusion barrier layer is formed over at least a portion of the surface. The...
6130481 Semiconductor integrated circuit interconnection structures and method of making the interconnection structures  
A semiconductor integrated circuit structure includes a semiconductor substrate; an electronic element disposed in the substrate; a first electrically insulating layer disposed on the substrate and...
6111298 Etch stop layer formed within a multi-layered gate conductor to provide for reduction of channel length  
A process is provided for forming a transistor gate conductor having an etch stop arranged at a depth below its upper surface such that the lateral width of the gate conductor above the etch stop...
6093966 Semiconductor device with a copper barrier layer and formation thereof  
A method of forming a semiconductor device by first providing a substrate in a processing chamber. The substrate has an insulating layer and an opening in the insulating layer. A copper barrier...
6056392 Method of producing recording head  
A recording head has a liquid emission section with an orifice for emitting ink, an electro-thermal transducer producing thermal energy for ink emission and a functional element electrically...
6040604 Semiconductor component comprising an electrostatic-discharge protection device  
A semiconductor component (10) includes a substrate (11), doped regions (15, 20) in the substrate (11), interconnect layers (23, 26, 29) coupled to one of the doped layers, and dielectric layers...
5952721 Semiconductor device having oxygen-doped silicon layer so as to restrict diffusion from heavily doped silicon layer  
A phosphorous doped amorphous silicon storage node electrode is treated with heat so as to be converted into a phosphorous doped polysilicon storage electrode, and the heat causes the phosphorous...
5939787 Semiconductor device having a multi-layer contact structure  
A semiconductor device and manufacturing method thereof having a diffusion barrier layer formed on a semiconductor wafer, whose surface region is provided with a silylation layer, wherein the...
5760476 Interconnect run between a first point and a second point in a semiconductor device for reducing electromigration failure  
In a first approach, an interconnect structure (10) reduces peak localized interconnect current density by distributing current flow around the perimeter (22) of an interlevel connector (14) in a...
5710461 SRAM cell fabrication with interlevel dielectric planarization  
A 4-T SRAM cell in which two layers of permanent SOG (with an intermediate oxide layer) are used to provide planarization between the first and topmost poly layers.
5614767 Alignment accuracy check pattern  
An alignment accuracy check pattern includes a contact hole formed in an insulating film on a major surface of a semiconductor substrate in a region different from an element region, and a...
5570119 Multilayer device having integral functional element for use with an ink jet recording apparatus, and recording apparatus  
A device for use with a liquid jet recording head, and such a head, include a substrate having a semiconductor functional element, an electrothermal transducer electrically connected to the...
5565708 Semiconductor device comprising composite barrier layer  
A semiconductor device comprising conductors electrically connected through a contact hole interlayer insulation layer with a trilayer barrier layer comprising a titanium silicide layer, titanium...
5414301 High temperature interconnect system for an integrated circuit  
A semiconductor integrated circuit device is provided with an electrical interconnect system which is stable at high temperatures. The interconnect system employs refractory metal compounds which...
5406121 Semiconductor device having improved interconnection wiring structure  
Disclosed herein is a semiconductor device having a substrate, an insulating layer covering the substrate, a plurality of wiring layer formed on the insulating layer, each wiring layer having a top...
5395457 Photovoltaic device and method of manufacturing the same  
A photovoltaic device having a tab soldered onto it for modularization, includes a first conductivity type crystalline semiconductor layer, a collector electrode electrically connected to the tab...
5380371 Photoelectric conversion element and fabrication method thereof  
A thin film solar cell having a semiconductor layer deposited on a substrate is composed of a passivation layer made of a polymer resin coated on the upper portion of the semiconductor layer, and...
5378652 Method of making a through hole in multi-layer insulating films  
A semiconductor device with an electrode wiring structure comprises at least one diffused region provided in a semiconductor substrate, a silicon oxide layer covering the substrate surface, a...
5360996 Titanium nitride/titanium silicide multiple layer barrier with preferential (111) crystallographic orientation on titanium nitride surface  
A process is described for forming, over a silicon surface, a titanium nitride barrier layer having a surface of (111) crystallographic orientation. The process comprises: depositing a first...
5319227 Low-leakage JFET having increased top gate doping concentration  
A low-leakage-current JFET having electrically isolated top and bottom gates. The structure employs enclosed geometry wherein one source/drain region fully surrounds the other source/drain region....
5315150 Semiconductor device and method of manufacturing the same  
A semiconductor device including a MOS element having a buried contact structure. The buried contact structure includes a first contact diffused region formed by diffusion from a polycrystalline...
5309023 Contact structure for interconnection in semiconductor devices and manufacturing method thereof  
A contact structure for interconnection in semiconductor devices provides electrical contact between an impurity-diffused region formed in a silicon substrate and a polycrystalline silicon layer...
5293073 Electrode structure of a semiconductor device which uses a copper wire as a bonding wire  
A semiconductor device comprises a semiconductor substrate, a first insulation film formed on the semiconductor substrate, a metal film for forming a bonding pad on the first insulation film, and a...
5281854 Integrated circuit aluminum contact structure to silicon device regions  
A structure formed by the method of forming a highly conductive electrical contact to a semiconductor region of an integrated circuits device is described. An opening to the semiconductor region is...
5243219 Semiconductor device having impurity diffusion region formed in substrate beneath interlayer contact hole  
A semiconductor device includes an impurity doped polycrystalline silicon layer formed on a first conductivity type semiconductor substrate with an oxide film provided therebetween, an interlayer...
5235210 Field effect transistor  
An SB FET comprising source and drain regions formed in the surface of a gallium arsenide (GaAs) substrate, and a channel region formed between the source and drain regions. The gate electrode of...
5175608 Method of and apparatus for sputtering, and integrated circuit device  
A thin film forming method and apparatus, wherein a negative voltage is applied alternately to a target and a substrate to perform film formation and reverse sputter alternately. Further, a coil is...
4985739 Low-leakage JFET  
A low-leakage-current JFET having electrically isolated top and bottom gates. The structure employs enclosed geometry wherein one source/drain region fully surrounds the other source/drain region....
4980751 Electrical multilayer contact for microelectronic structure  
An electrical contact between two film members that is stable over all conditions encountered in processing and over the device lifetime. The contact has a central multi-element diffusion barrier...
4922320 Integrated circuit metallization with reduced electromigration  
The specification discloses a method and a device wherein circuit elements (10) are formed on the surface of a semiconductor body (12). A layer of oxide (22) is applied over the circuit element...
4914500 Method for fabricating semiconductor devices which include sources and drains having metal-containing material regions, and the resulting devices  
A new method for fabricating a semiconductor device, e.g., a MOS or MES IC, as well as the resulting device, are disclosed. In accordance with the new method, a semiconductor device is formed, at...
4860084 Semiconductor device MOSFET with V-shaped drain contact  
A concave portion having a V-shaped cross section is formed in a contact region of a p-type silicon substrate. The contact region is defined by a hole formed in an insulative layer formed over the...
4837183 Semiconductor device metallization process  
A metallization process for semiconductor devices wherein the metal deposition steps are performed at higher wafer temperatures than subsequent processing steps. The correlation between wafer...
4824803 Multilayer metallization method for integrated circuits  
Metal contacts and interconnections for semiconductor integrated circuits are fabricated through the deposition of a sandwich structure of metal. The bottom layer of a refractory metal prevents...
4821089 Protection of IGFET integrated circuits from electrostatic discharge  
Integrated circuits implemented in insulated gate (e.g., CMOS) technology have been protected from electrostatic discharge (ESD) by a metal gate field effect transistor. It has been recognized that...
4818721 Ion implantation into In-based group III-V compound semiconductors  
Implantation of a Group V ion species (e.g., phosphorus or arsenic) into an In-based Group III-V compound semiconductor (e.g., InP, InGaAs) followed by implantation of Be ions produces a shallow...
4803541 Semiconductor device  
A semiconductor device wherein a semiconductor region which is electrically floating is provided in the main surface of a semiconductor substrate under a bonding pad. This construction helps...
4734383 Fabricating semiconductor devices to prevent alloy spiking  
After contact holes for the P- and N-type source or drain regions of P- and N-channel MOSFETs have been made at a common step, an N-type impurity is ion-implanted into at least the N-type source or...
4301188 Process for producing contact to GaAs active region  
The stability of semiconductor devices such as gallium arsenide field effect transistors are significantly improved by controlling the process leading to the production of the drain contact. The...
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