|
Match
|
Document |
Document Title |
|
|
8183088 |
Semiconductor die package and method for making the same
Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an...
|
|
|
8174131 |
Semiconductor device having a filled trench structure and methods for fabricating the same
Methods are provided for packaging a semiconductor die having a first surface. In accordance with an exemplary embodiment, a method comprises the steps of forming a trench in the first surface of...
|
|
|
8143707 |
Semiconductor device
A semiconductor device includes a circuit base including an inner lead portion and an outer lead portion. The inner lead portion has a plurality of inner leads. At least part of the inner leads is...
|
|
|
8115284 |
Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board and electronic instrument
A semiconductor device with its package size close to its chip size has a stress absorbing layer, allows a patterned flexible substrate to be omitted, and allows a plurality of components to be...
|
|
|
8110913 |
Integrated circuit package system with integral inner lead and paddle
An integrated circuit package system includes: fabricating a lead frame including: providing inner leads having an inner lead pitch of progressive length, forming a lead shoulder, on the inner...
|
|
|
8106493 |
Semiconductor device package having features formed by stamping
Embodiments of the present invention relate to the use of stamping to form features on a lead frame of a semiconductor device package. In one embodiment, portions of the lead frame such as pins are...
|
|
|
8097934 |
Delamination resistant device package having low moisture sensitivity
A lead frame and package construction configured to attain a thin profile and low moisture sensitivity. Lead frames of this invention may include a die attach pad having a die attachment site and...
|
|
|
8058719 |
Integrated circuit with flexible planer leads
A microelectronic device including a microelectronic circuit and at least one planar flexible lead. These planar flexible leads are adapted to bend and flex during mechanical stress allow direct...
|
|
|
8021929 |
Apparatus and method configured to lower thermal stresses
An apparatus and a method configured to lower thermal stress is disclosed. One embodiment provides a semiconductor chip, a lead frame and a layer structure. The layer structure includes at least a...
|
|
|
8022509 |
Crack stopping structure and method for fabricating the same
A crack stopping structure is disclosed. The crack stopping structure includes a semiconductor substrate having a die region, a die seal ring region, and a scribe line region; a metal interconnect...
|
|
|
8017445 |
Warpage-compensating die paddle design for high thermal-mismatched package construction
A method and packaging for semiconductor devices and integrated circuits is disclosed that eliminates warpage stress on packages caused by coefficient of thermal expansion (CTE) mismatch between...
|
|
|
8018042 |
Integrated circuit with flexible planar leads
A microelectronic device including a microelectronic circuit and at least one planar flexible lead. These planar flexible leads are adapted to bend and flex during mechanical stress, allowing...
|
|
|
7982309 |
Integrated circuit including gas phase deposited packaging material
An integrated circuit includes a substrate including an active area and a gas phase deposited packaging material encapsulating the active area.
|
|
|
7977774 |
Fusion quad flat semiconductor package
A semiconductor package which includes a generally planar die paddle defining multiple peripheral edge segments and a plurality of leads which are segregated into at least two concentric rows....
|
|
|
7977775 |
Semiconductor device and manufacturing method of the same
The present invention enables improvement of bonding reliability of the conductive adhesive interposed between a semiconductor chip and a die pad portion. Provided is a semiconductor device, in...
|
|
|
7977160 |
Semiconductor devices having stress relief layers and methods for fabricating the same
Methods are provided for fabricating a semiconductor device. In accordance with an exemplary embodiment, a method comprises the steps of providing a semiconductor die having a conductive terminal,...
|
|
|
7968981 |
Inline integrated circuit system
An integrated circuit package system including: providing a leadframe with an integrated circuit mounted thereover; encapsulating the integrated circuit with an encapsulation; mounting an etch...
|
|
|
7955884 |
Semiconductor packages
A semiconductor package includes a semiconductor chip including a semiconductor substrate and a plurality of cell transistors arranged on the semiconductor substrate. Channel regions of the cell...
|
|
|
7947534 |
Integrated circuit packaging system including a non-leaded package
An integrated circuit package system is provided including: forming a plurality of leads with a predetermined thickness and a predetermined interval gap between each of the plurality of leads;...
|
|
|
7943961 |
Strain bars in stressed layers of MOS devices
A semiconductor structure includes an active region; a gate strip overlying the active region; and a metal-oxide-semiconductor (MOS) device. A portion of the gate strip forms a gate of the MOS...
|
|
|
7928540 |
Integrated circuit package system
An integrated circuit package system is provided including forming an external interconnect having a lead body and a lead tip, forming a lead protrusion in the lead tip, connecting a device and the...
|
|
|
7911062 |
Electronic component with varying rigidity leads using Pb-free solder
The present invention proposes a semiconductor device including a semiconductor chip having a plurality of electrodes, a plurality of leads electrically connected to the plurality of electrodes of...
|
|
|
7911039 |
Component arrangement comprising a carrier
A component arrangement comprising a carrier, a component in a housing with electrical contacts and a moulding compound that encloses the carrier, the semiconductor component in the housing and the...
|
|
|
7888782 |
Apparatus and method configured to lower thermal stresses
An apparatus and a method configured to lower thermal stress is disclosed. One embodiment provides a semiconductor chip, a lead frame and a layer structure. The layer structure includes at least a...
|
|
|
7880278 |
Integrated circuit having stress tuning layer
Warpage and breakage of integrated circuit substrates is reduced by compensating for the stress imposed on the substrate by thin films formed on a surface of the substrate. Particularly...
|
|
|
7863108 |
Integrated circuit packaging system with etched ring and die paddle and method of manufacture thereof
A method of manufacture of an integrated circuit packaging system is provided including: forming a D-ring includes half etching a paddle, etching a ring, and etching a tie bar. The tie bar is...
|
|
|
7863737 |
Integrated circuit package system with wire bond pattern
An integrated circuit package system including providing a plurality of substantially identical package leads formed in a single row, and attaching bond wires having an offset on adjacent locations...
|
|
|
7859089 |
Copper straps
A copper strap for a semiconductor device package having a contact electrically connected to a die electrode, a leg portion electrically connected to a lead frame, a web portion positioned between...
|
|
|
7847391 |
Manufacturing method for integrating a shunt resistor into a semiconductor package
An integrated circuit package that comprises a lead frame, an integrated circuit located on the lead frame and a shunt resistor coupled to the lead frame and to the integrated circuit. The shunt...
|
|
|
7838339 |
Semiconductor device package having features formed by stamping
Embodiments of the present invention relate to the use of stamping to form features on a lead frame of a semiconductor device package. In one embodiment, portions of the lead frame such as pins are...
|
|
|
7839003 |
Semiconductor device including a coupling conductor having a concave and convex
While a semiconductor device is provided with a plurality of element electrodes 5 formed on a semiconductor element 4 and a plurality of lead terminal electrodes 6 formed on a lead frame, the...
|
|
|
7834432 |
Chip package having asymmetric molding
A chip package having asymmetric molding includes a lead frame, a chip, an adhesive layer, bonding wires and a molding compound. The lead frame includes a turbulent plate and a frame body having...
|
|
|
7820480 |
Lead frame routed chip pads for semiconductor packages
A redistributed lead frame for use in a molded plastic semiconductor package (38) is formed from an electrically conductive substrate by a sequential metal removal process. The process includes:...
|
|
|
7821112 |
Semiconductor device with wire-bonding on multi-zigzag fingers
A semiconductor device having linear zigzag(s) for wire bonding is revealed, primarily comprising a chip, a plurality of leads made of a lead frame and a plurality of bonding wires electrically...
|
|
|
7812463 |
Packaging integrated circuits for high stress environments
One aspect of the invention pertains to a semiconductor package suitable for use in high stress environments, such as ones involving high pressures, temperatures and/or corrosive substances. In...
|
|
|
7808088 |
Semiconductor device with improved high current performance
A semiconductor device comprises a die having a first surface and a second surface, a first leadframe connected to the first surface and the second surface, and a second leadframe connected to the...
|
|
|
7808086 |
Lead frame and manufacturing method thereof, and semiconductor apparatus and manufacturing method thereof
The present invention includes a plurality of mounting portions on which a semiconductor element is mounted, a plurality of electrodes to which the semiconductor elements that are mounted on each...
|
|
|
7800219 |
High-power semiconductor die packages with integrated heat-sink capability and methods of manufacturing the same
An exemplary semiconductor die package of the invention has a metal-oxide substrate disposed between a first surface of a semiconductor die and a heat-sinking component, with a conductive die clip...
|
|
|
7791178 |
Lead frame unit, semiconductor package having a lead frame unit, stacked semiconductor package having a semiconductor package and methods of manufacturing the same
A lead frame unit, a semiconductor package having a lead frame unit, a stacked semiconductor package having a semiconductor package, and methods of manufacturing the same are provided. The lead...
|
|
|
7786588 |
Composite interconnect structure using injection molded solder technique
Composite interconnect structure forming methods using injection molded solder are disclosed. The methods provide a mold having at least one opening formed therein with each opening including a...
|
|
|
7786554 |
Stress-free lead frame
The present invention relates to a stress-free lead frame (1) for a semiconductor. The stress-free lead frame (1) is provided with a stress-relief means (15) and an interlocking means (16) at the...
|
|
|
7781851 |
Semiconductor device having reduced die-warpage and method of manufacturing the same
A semiconductor device and a method of manufacturing the same reduce die-warpage. The semiconductor device includes a substrate and a first layer of material extending substantially over the entire...
|
|
|
7772681 |
Semiconductor die package and method for making the same
Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an...
|
|
|
7767912 |
Integrated circuit carrier arrangement with electrical connection islands
An integrated circuit carrier arrangement includes a printed circuit board (PCB), a receiving plate to which an integrated circuit can be mounted, and a carrier fast with the PCB. The carrier has a...
|
|
|
7750443 |
Semiconductor device package
A surface of a lead frame of a semiconductor device package, on which a semiconductor chip is mounted, is formed to have a mesh structure, whereby a connecting area between the lead frame and a...
|
|
|
7745913 |
Power semiconductor component with a power semiconductor chip and method for producing the same
A power semiconductor component includes at least one power semiconductor chip and surface-mountable external contacts. The power semiconductor chip includes large-area contact areas on its top...
|
|
|
7745912 |
Stress absorption layer and cylinder solder joint method and apparatus
An apparatus, method, and system for providing a stress absorption layer for integrated circuits includes a stiffening layer adapted to limit flexing. A compliance layer is physically associated...
|
|
|
7714417 |
Substrate for mounting semiconductor element and method of manufacturing the same
The present invention provides a semiconductor element mounting substrate 101 including: a base substrate 1 having a region 2 for mounting a semiconductor element 11, the region 2 being set on the...
|
|
|
7709936 |
Module with carrier element
The invention relates to a module comprising a carrier element having a lower stiffness or a different structure in a first region than in a second region, and also comprising a component applied...
|
|
|
7679145 |
Transistor performance enhancement using engineered strains
A semiconductor substrate having metal oxide semiconductor (MOS) devices, such as an integrated circuit die, is mechanically coupled to a stress structure to apply a stress that improves the...
|