|
Match
|
Document |
Document Title |
|
|
5777374 |
Integrated circuit interconnect structure with back reflection suppressing electronic "speed bumps"
A polysilicon interconnect is formed on a microelectronic circuit substrate for conducting signals from a driver to a non-polycrystalline silicon contact which has higher impedance than the...
|
|
|
5777540 |
Encapsulated fuse having a conductive polymer and non-cured deoxidant
A simplified method of manufacturing an electrothermal fuse includes the steps of screening conductive epoxy onto fuse link termination pads, placing a metal alloy fuse link into the conductive...
|
|
|
5760464 |
Semiconductor device
A semiconductor device has a semiconductor chip with a plurality of pads, an inner lead which is connected to a plurality of pads by a plurality of bonding wires and which has a broken part...
|
|
|
5747868 |
Laser fusible link structure for semiconductor devices
An improved laser fusible link structure for semiconductor devices (200) and method of manufacturing thereof (10) is disclosed. A first conductive layer is patterned to create a laser fuse (202)...
|
|
|
5729048 |
Cmos ic device suppressing spike noise
A CMOS IC device operating at a frequency of 300 MHz or higher includes a power supply wiring for interconnecting one of circuit elements and a power supply pad, and a phase-shifting split wiring...
|
|
|
5729041 |
Protective film for fuse window passivation for semiconductor integrated circuit applications
An integrated circuit includes a conductive fusible link that may be blown by heating with laser irradiation, The integrate circuit comprises a silicon substrate; a first insulating layer; a...
|
|
|
5723898 |
Array protection devices and method
The present disclosure sets forth an improved integrated circuit in which circuit elements, adjacent to a fuse, are protected by barriers positioned adjacent the fuse. In the improved integrated...
|
|
|
5698894 |
Double mask hermetic passivation structure
A passivation structure is formed using two passivation layers and a protective overcoat layer using two masking steps. The first passivation layer is formed over the wafer and openings are...
|
|
|
5698895 |
Silicon segment programming method and apparatus
The present invention is a method and apparatus for programming a stack of segments wherein each segment includes a plurality of die which are interconnected through metal interconnects patterned...
|
|
|
5691566 |
Tapered three-wire line vertical connections
An electrical connection is provided between a 3-wire transmission line buried in a dielectric substrate and corresponding first, second and third conductive pads formed on a substrate surface. The...
|
|
|
5672905 |
Semiconductor fuse and method
A semiconductor fuse and method for fabricating the same An insulating layer is provided and a trench formed therein. A fusible link is then formed across the insulating layer and trench and...
|
|
|
5670815 |
Layout for noise reduction on a reference voltage
A layout portion (20) has a first portion (25), and a second portion (55). In the first portion (25), a reference voltage line (27) is disposed between two V DD power supply lines (26, 30) for a...
|
|
|
5663590 |
Product of process for formation of vias (or contact openings) and fuses in the same insulation layer with minimal additional steps
A process and resulting product are described for forming an integrated circuit structure with horizontal fuses on an insulation layer formed over other portions of the integrated circuit structure...
|
|
|
5652459 |
Moisture guard ring for integrated circuit applications
An improved structure and method for forming an integrated circuit guard ring which prevents contamination/moisture from diffusing through a fuse opening, in the insulating layer(s), to device...
|
|
|
5648661 |
Integrated circuit wafer comprising unsingulated dies, and decoder arrangement for individually testing the dies
Unsingulated dies on a wafer may be individually electronically selected using various "electronic mechanisms" on the wafer. Conductive lines extend on the wafer from the electronic mechanism to...
|
|
|
5623160 |
Signal-routing or interconnect substrate, structure and apparatus
Method and apparatus for interconnecting integrated circuits (ICs) are described. The invented lattice preferably is formed in a plural-layer structure whereby each required interconnect signal has...
|
|
|
5606197 |
High capacitance capacitor in an integrated function block or an integrated circuit
A method for creating a MOS-type capacitor structure in function blocks or integrated circuits. Each block or cell is provided with capacitors for decoupling purposes under the board metal supply...
|
|
|
5598029 |
Power supply wiring for semiconductor device
Ground lines 2 are disposed so as to sandwich a power supply line 1. A gate oxide film 3 and a gate 4 are formed below the power supply line 1. An n-type area 8 is formed adjacent to the end of the...
|
|
|
5572050 |
Fuse-triggered antifuse
A programmable integrated circuit for forming conductive links includes a heat-generating programming structure through which current flows upon application of a programming voltage to heat the...
|
|
|
5528072 |
Integrated circuit having a laser connection of a conductor to a doped region of the integrated circuit
The conductor 15 to be connected to the doped region 12 of the substrate 11 has an edge 15a at which the laser beam 20 is aimed, regulated such as to definitively create a zone of low electrical...
|
|
|
5477079 |
Power source noise suppressing type semiconductor device
A power source noise suppressing type semiconductor device has: a semiconductor chip formed therein with a first circuit and a second circuit, the semiconductor chip having a plurality of pads on...
|
|
|
5465004 |
Programmable semiconductor integrated circuits having fusible links
The size of a fusible link (22 C F ) created from part of a metal layer (22) is controlled by an oxidation performed in a deposition chamber that is also used for depositing a dielectric layer (30)...
|
|
|
5459342 |
Field programmable gate array with spare circuit block
A field programmable gate array, comprises: a plurality of circuit blocks each having logic circuits; at least one spare circuit block having logic circuits; a set of interconnections including at...
|
|
|
5420455 |
Array fuse damage protection devices and fabrication method
The present disclosure sets forth an improved integrated circuit in which circuit elements, adjacent to a fuse, are protected by barriers positioned adjacent the fuse. In the improved integrated...
|
|
|
5410163 |
Semi-conductor integrated circuit device including connection and disconnection mechanisms to connect and disconnect monitor circuit and semiconductor integrated circuit from each other
A monitor circuit provided in a chip in which a semiconductor integrated circuit is formed. Connection mechanisms and disconnection mechanisms are connected in series in wirings connected to the...
|
|
|
5389814 |
Electrically blowable fuse structure for organic insulators
An electrically blowable fuse structure usable with organic insulators in microelectronic parts is provided. The fuse structure is made of a first heat resistant member, a fusing element and a...
|
|
|
5331195 |
Fuse construction of a semiconductor device
At least one fusing electrode charging electrode portion is connected to an intermediate portion of a fuse body of a fuse that has the fuse body and connecting end electrode portions provided at...
|
|
|
5329152 |
Ablative etch resistant coating for laser personalization of integrated circuits
A programmable integrated circuit for prototyping applications including a first patterned metal layer, an insulation layer formed over the first metal layer and a second patterned metal layer...
|
|
|
5309024 |
Multilayer package
The present invention provides a multilayer ceramic package, which comprises a conductive layer, formed like a square layer, applying a power voltage V DD or a ground voltage V SS to a...
|
|
|
5306949 |
Transistor module having external lead terminal with transient voltage suppression
In an external lead terminal 5 of a transistor module, an intermediate terminal portion 6 and an external lead terminal 8 are conductively connected to each other via a U-shaped intermediate...
|
|
|
5303199 |
Redundant memory device having a memory cell and electrically breakable circuit having the same dielectric film
An easily circuit-programmable semiconductor device which comprises a dynamic random access memory (DRAM) unit, a redundancy circuit and a connection between them, the DRAM unit having as a...
|
|
|
5299151 |
Method for writing into semiconductor memory
A method is provided for writing into a semiconductor memory which includes a MOS transistor formed on a semiconductor substrate and an anti-fuse formed of an insulating film and an upper electrode...
|
|
|
5264725 |
Low-current polysilicon fuse
A submicron-width fuse element is disclosed that protects peripheral DRAM chip devices from low current failures below the range of metal fuse elements. In a specific application, the fuse elements...
|
|
|
5260597 |
Routing structure for a customizable integrated circuit
A selectably customizable semiconductor device including a first metal layer disposed in a first plane and including first elongate strips extending parallel to a first axis, a second metal layer...
|
|
|
5256899 |
Integrated circuit fuse link having an exothermic charge adjacent the fuse portion
A fuse link includes a fuse portion and a exothermic charge adjacent the fuse portion for blowing the fuse portion upon application of a triggering current to the fuse link.
|
|
|
5200364 |
Packaged integrated circuit with encapsulated electronic devices
An integrated circuit device is disclosed. The device includes a first leadframe power supply bus and a second leadframe power supply bus that each have portions separate from and adjacent to one...
|
|
|
5144412 |
Process for manufacturing plastic pin grid arrays and the product produced thereby
A pin grid array package is provided. An array of terminal pins pass through apertures formed in an interconnect tape. The terminal pins are electrically connected to circuit traces formed on...
|
|
|
5070392 |
Integrated circuit having laser-alterable metallization layer
An integrated circuit and a method of altering such an integrated circuit (e.g., during final testing of the circuit) are such that the method can be used to program a circuit, wire around...
|
|
|
5068706 |
Semiconductor device with fuse function
A semiconductor device includes a radiation plate, first and second conductive patterns formed on one surface of the radiation plate, a first semiconductor element fixed on and connected to the...
|
|
|
5053383 |
Method of reducing critical current density of oxide superconductors by radiation damage
The critical current density J c of a superconductive oxide film can be tailored, without substantial change in the critical temperature T c (R0), by introduction of radiation damage into the...
|
|
|
5043792 |
Integrated circuit having wiring strips for propagating in-phase signals
An integrated circuit is fabricated on a semiconductor substrate and comprises a plurality of component circuits having first and second circuits respectively serving as signal sources and a third...
|
|
|
5040049 |
Semiconductor device and method of manufacturing a semiconductor device
The invention relates to a semiconductor device comprising a silicon body (1) provided with a conductor pattern (4, 5) consisting of a contact layer (4) and an aluminium layer (5). Contact layers...
|
|
|
5027174 |
Semiconductor integrated circuit device with improved resistance against electrostatic noise
A semiconductor integrated circuit device has an internal circuit formed on a semiconductor substrate and a first conductive layer connected to an electrode pad for communicating signals with the...
|
|
|
5017510 |
Method of making a scalable fuse link element
A fuse link (50) is formed using a method which offers greater scalability of the general conductor system used to wire the device. An oxide mask (36) having the shape of a desired fuse link is...
|
|
|
5011791 |
Fusible link with built-in redundancy
A fusible link is fabricated using sidewall spacer technology. The fusible link of the present requires low fusing power because a fusible link having a small cross-sectional area is obtainable. A...
|
|
|
5006918 |
Floating orthogonal line structure for X-Y wiring planes
Far-end noise caused by coupling between active and quiet signal lines of wiring planes of an integrated circuit chip or chip carrier is reduced by providing floating crossing lines in wiring...
|
|
|
5003371 |
Fuse-melting device
The melting of a fuse of a CMOS type integrated circuit is caused by using the existence of a stray thyristor created in the neighborhood of the boundaries of pads made in a substrate. This stray...
|
|
|
4994902 |
Semiconductor devices and electronic system incorporating them
An electronic system having a first and a second semiconductor device acting as a microprocessor and a coprocessor, respectively, disposed linearly on a mounting board. The external pins common to...
|
|
|
4993954 |
Device for interconnection between and integrated circuit and an electrical circuit
An object of the invention is a device for interconnection between an integrated circuit and an electrical circuit, such as a printed circuit. This device has, depending on the desired...
|
|
|
4970686 |
Semiconductor memory cells and semiconductor memory device employing the semiconductor memory cells
A spare memory cell comprises a read FET (Field Effect Transistor), a fusing FET and a current fuse. The FETs are connected in series between a read data line and a low voltage source. The fuse is...
|