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7151306 Electronic part, and electronic part mounting element and an process for manufacturing such the articles  
A surface of an external electrode 3 of an electronic part 4 is formed with a coating containing resin ingredient. Thereby, adhesion strength and reliability may be significantly improved in...
7042049 Composite etching stop in semiconductor process integration  
A new method of forming a composite etching stop layer is described. An etching stop layer is deposited on a substrate wherein the etching stop layer is selected from the group consisting of:...
6953961 DRAM structure and fabricating method thereof  
A dynamic random access memory (DRAM) structure and a fabricating process thereof are provided. In the fabricating process, a channel region is formed with a doped region having identical...
6914320 Bilayer HDP CVD/PE CVD cap in advanced BEOL interconnect structures and method thereof  
An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a bilayer diffusion barrier or cap, where the first cap layer is formed of a dielectric material...
6667553 H:SiOC coated substrates  
This invention pertains to a method for producing hydrogenated silicon oxycarbide (H:SiOC) films having low dielectric constant and a light transmittance of 95% or more for light with a wavelength...
6563197 MOSgated device termination with guard rings under field plate  
Guard ring diffusions in the termination of a MOSgated device are laterally spaced from one another and are disposed beneath and are insulated from the termination field plate which extends from...
6501155 Semiconductor apparatus and process for manufacturing the same  
To provide a semiconductor apparatus that secures high ESD protection capability and yet reduces leak current. Cut sections 64 - 1 and 64 - 2 are provided in end sections of a second edge 62 ...
6465867 Amorphous and gradated barrier layer for integrated circuit interconnects  
An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate....
6452285 Fabrication of standard defects in contacts  
Various circuit devices for contact defect inspection and methods of fabrication and use thereof are provided. In one aspect, a circuit device is provided that includes a substrate and an...
6333548 Semiconductor device with etch stopping film  
There are provided a semiconductor device and a method for manufacturing the same in which a thin film polysilicon film having a small parasitic capacitance which is required for attaining the...
6215167 Power semiconductor device employing field plate and manufacturing method thereof  
A power semiconductor device having an breakdown voltage improving structure and a manufacturing method thereof are provided. A collector region and a base region create a pn junction between them....
6211541 Article for de-embedding parasitics in integrated circuits  
An article for de-embedding parasitics and/or acting as an on-wafer calibration standard is disclosed. In particular, some articles in accordance with the present invention provide structures on...
6194750 Integrated circuit comprising means for high frequency signal transmission  
An integrated circuit is disclosed that comprises structures that confine, shield and/or manipulate the electric fields generated within the integrated circuit so as to improve the performance of...
6153920 Process for controlling dopant diffusion in a semiconductor layer and semiconductor device formed thereby  
A semiconductor device having a carbon-containing region with an advantageous concentration profile is disclosed. The carbon is introduced into a region of the substrate and at a depth below the...
6084263 Power device having high breakdown voltage and method of manufacturing the same  
The main characteristic feature of the invention is to prevent a leakage current from flowing when a planar type semiconductor device having a high breakdown voltage is reverse-biased. For example,...
6064110 Digital circuit with transistor geometry and channel stops providing camouflage against reverse engineering  
An integrated digital circuit is protected from reverse engineering by fabricating all transistors of like conductivity with a common size and geometric layout, providing a common layout for...
5712492 Transistor for checking radiation-hardened transistor  
A checking transistor for checking selected regions a semiconductor substrate containing radiation-hardened semiconductor circuitry having a plurality of transistors according to the present...
5641982 High voltage mosfet with an improved channel stopper structure  
The present invention provides a MOS field effect transistor comprising: a semiconductor substrate having a first conductivity type; source/drain regions of a second conductivity type; lightly...
5631496 Semiconductor component having a passivation layer and method for manufacturing same  
A semiconductor component has a semiconductor body with at least on pn-junction therein, extending to the surface of the semiconductor body, and has a passivation layer composed of boron-doped,...
5508555 Thin film field effect transistor having a doped sub-channel region  
A thin film field effect transistor (1) is formed by an insulating substrate (2,3) carrying a semiconductor layer (4) having a polycrystalline channel region (5) which is passivated to reduce the...
5483096 Photo sensor  
A photo sensor comprises a semiconductor substrate, a bipolar photo transistor having an emitter region, a base region and a collector region which is formed in the surface region of the...
5350942 Low resistance silicided substrate contact  
Low resistance contacts for establishing an electrical pathway to an integrated surface substrate are provided. The pathway is formed by the connection of a p+ doped channel stop region with a p+...
5311052 Planar semiconductor component with stepped channel stopper electrode  
Semiconductor component, including a semiconductor body having an edge, a surface, a substrate of a first given conductivity type, at least one zone being embedded in a planar manner in the...
5298770 Power switching MOS transistor  
A power switching metal oxide semiconductor (PSMOS) transistor comprises a plurality of vertical double-diffused MOS (VDMOS) transistors formed on a semiconductive substrate of a first type...
5298789 Semiconductor component for a high blocking bias  
Semiconductor components having planar structures such as MOSFETs, bipolar transistors, and isolated gate bipolar transistors are provided with field plates (5) and, potentially, with guard rings...
5262672 Apparatus for improvement of interconnection capacitance  
A method and apparatus for reducing interconnection capacitance. A lightly doped buried layer is provided in or on a substrate below a field oxide region. The capacitance of an interconnect on the...
5192993 Semiconductor device having improved element isolation area  
A semiconductor device of the present invention is disclosed which includes a semiconductor device of a predetermined conductivity type having a predetermined impurity concentration, a source/drain...
5049964 Bipolar transistor and method of manufacturing the same  
A bipolar transistor includes collector, base and emitter regions. The collector region consists of a first semiconductor region of a first conductivity type and formed in contact with a surface of...
4972242 Silicon avalanche photodiode with low multiplication noise  
There is provided an n + -p-π-p + APD having a shallow and abrupt p-n junction located about 1 to 2 μm into the APD and having a p-type conductivity region containing acceptors in an...
4816882 Power MOS transistor with equipotential ring  
A process for manufacturing a DMOS transistor in accordance with the present invention includes the steps of forming a layer of gate insulation (12, 14) on an N type substrate (10). A layer of...
4753896 Sidewall channel stop process  
A new way of making sidewall channel stops for silicon on insulator devices (including silicon on oxide, silicon on nitride, and silicon on sapphire devices). While the moat regions 11, 13 (where...
4729964 Method of forming twin doped regions of the same depth by high energy implant  
First conductivity type impurity ions are implanted at a predetermined depth all over a region where impurity ions are to be implanted, and second conductivity type impurity ions are implanted in a...
4717683 CMOS process  
A process is disclosed for fabricating complementary insulated gate field effect transistors including doped field isolation regions and optional punch through protection. In one embodiment of...
4691224 Planar semiconductor device with dual conductivity insulating layers over guard rings  
A planar semiconductor device having a main p-n junction surrounded by at least one guard ring covered with an insulating layer having an opening is provided with an electrode electrically...
4666556 Trench sidewall isolation by polysilicon oxidation  
Disclosed is a process of growing a conformal and etch-resistant silicon dioxide on a surface by forming a conformal layer of polysilicon and subjecting the polysilicon to thermal oxidation to...
4618875 Darlington transistor circuit  
A Darlington transistor circuit having a power transistor and a driver transistor is proposed. The two transistors are monolithically integrated in a common substrate (10) by a planar process, the...
4613885 High-voltage CMOS process  
A high-voltage CMOS process, providing (for 5 micron geometries) both field thresholds and junction breakdowns in excess of 20 volts, wherein only one channel stop implant is used. A double-well...
4573257 Method of forming self-aligned implanted channel-stop and buried layer utilizing non-single crystal alignment key  
A process is described for fabricating self-aligned buried doped regions in semiconductor devices and integrated circuits which avoids any need for delineation of the buried doped regions in the...
4496963 Semiconductor device with an ion implanted stabilization layer  
A semiconductor device wherein surface stabilization is provided by a shallow layer of ion implanted doping material on the surface of the semiconductor and beneath the passivating oxide layer. One...
4485393 Semiconductor device with selective nitride layer over channel stop  
A semiconductor device comprises a semiconductor body of one conductivity type, at least one semiconductor region of the opposite conductivity type formed in the semiconductor body and having a...
4472874 Method of forming planar isolation regions having field inversion regions  
A method for manufacturing integrated circuit devices wherein semiconductor elements are isolated by insulation material comprising the following steps of: (a) providing a mask pattern on a...
4463368 Silicon avalanche photodiode with low k.sub.eff  
An n-p-π-p + Si avalanche photodiode wherein the number of acceptors introduced into a Si body to form the p-type conductivity region has been reduced and this region extends a distance greater...
4458260 Avalanche photodiode array  
The invention is an APD array having a plurality of p-n junctions. The p-n junctions comprise a plurality of separate regions which extend a distance into a semiconductor body from a surface...
4434543 Process for producing adjacent tubs implanted with dopant ions in the manufacture of LSI complementary MOS field effect transistors  
The invention provides a method for manufacturing adjacent tubs implanted with dopant material ions in the manufacture of LSI complementary MOS field effect transistor circuits (CMOS circuits), and...
4412242 Planar structure for high voltage semiconductor devices with gaps in glassy layer over high field regions  
Two gaps are placed in the reflowed phosphorus-doped silicon dioxide material overcoating of a planar high voltage semiconductor device to prevent polarization of the reflowed silox. The invention...
4411058 Process for fabricating CMOS devices with self-aligned channel stops  
An improved process is provided for fabricating CMOS (Complementary Metal Oxide Semiconductor) devices formed on a semiconductor substrate having n-channel and p-channel regions of n- and p-type...
4400716 Semiconductor device with glass layer contacting outer periphery of guard ring and adjacent substrate  
A semiconductor device with a planar p-n junction and a guard ring region, wherein an oxide film is covered on the surface between the p-n junction and the guard ring, and a glass film is formed on...
4312011 Darlington power transistor  
This invention relates to a Darlington power transistor which executes a stable operation and which demonstrates satisfactory characteristics, characterized in that respective base regions of a...
4235011 Semiconductor apparatus  
A method for fabricating a field-effect transistor device is provided with the device resulting having a relatively substantial capability to withstand reverse bias voltages. The device can also be...
4153904 Semiconductor device having a high breakdown voltage junction characteristic  
A semiconductor device having a p-n junction characterized by low electric field crowding and a resulting high avalanche breakdown voltage requirement. The semiconductor device is comprised of a...
Matches 1 - 50 out of 85 1 2 >