Matches 101 - 150 out of 234 < 1 2 3 4 5 >
Match Document Document Title
6297521 Graded anti-reflective coating for IC lithography  
A substantially continuously graded composition silicon oxycarbide (SiOC) antireflective coating (ARC) or antireflective layer (ARL) is interposed between a photoresist layer and an underlying...
6278174 Integrated circuit insulator and structure using low dielectric insulator material including HSQ and fluorinated oxide  
An intermetal level dielectric with two different low dielectric constant insulators: one for gap filling (140) within a metal level and the other (150) for between metal levels. Preferred...
6271593 Method for fabricating conductive components in microelectronic devices and substrate structures therefor  
A method and substrate structure for fabricating highly conductive components on microelectronic devices. In one embodiment in accordance with the principles of the present invention, a first...
6265758 Semiconductor active electrostatic device  
A semiconductor electrostatic device for producing an output electrostatic force includes an active element, an opposed field element and a control element. The active element has a semiconductor...
6261945 Crackstop and oxygen barrier for low-K dielectric integrated circuits  
A copper-interconnect, low-K dielectric integrated circuit has reduced corrosion of the interconnect when the crackstop next to the kerf is also used as the primacy barrier to oxygen diffusion...
6246105 Semiconductor device and manufacturing process thereof  
A semiconductor device having an insulation protection film with increased reliability and improved device characteristics, and a manufacturing method thereof which improves the planarization and...
6242355 Method for insulating metal conductors by spin-on-glass and devices made  
A method for insulating metal conductors by spin-on-glass in inter-metal dielectric layers and devices formed by such method are disclosed. In the method, an additional step of scrubber clean is...
6208015 Interlevel dielectric with air gaps to lessen capacitive coupling  
A reduced permittivity interlevel dielectric in a semiconductor device arranged between two levels of interconnect. The dielectric comprises a first dielectric layer preferably from a silane source...
6194784 Self-aligned contact process in semiconductor fabrication and device therefrom  
The encapsulation of gate stacks of a semiconductor device in an oxide insulative layer and in a silicon nitride etch-stop layer allows the formation of a contact filling for connection to...
6184572 Interlevel dielectric stack containing plasma deposited fluorinated amorphous carbon films for semiconductor devices  
An interlevel dielectric stack for use in semiconductor devices is provided. The interlevel stack includes a bottom adhesion layer, a middle layer composed of a fluorinated amorphous carbon film,...
6180507 Method of forming interconnections  
A method of forming interconnections is provided. A defined metal layer is formed as a metal line on a provided substrate. An oxide layer is formed on the metal layer and on the substrate. A...
6133619 Reduction of silicon oxynitride film delamination in integrated circuit inter-level dielectrics  
Outgassing from a dielectric gap fill layer, e.g., a low dielectric constant material such as HSQ, and attendant deformation or delamination of a barrier dielectric layer on an overlying patterned...
6124622 MIS transistor with a three-layer device isolation film surrounding the MIS transistor  
A device isolation film is formed on one major surface of a semiconductor substrate so as to surround a device formation region. The device isolation film consists of a first layer made of silicon...
6114747 Process design for wafer edge in VLSI  
A wafer structure and method of forming a wafer structure with all of the dielectric material and conducting material films removed from the outer periphery of the wafer in order to protect the...
6104081 Semiconductor device with semiconductor elements formed in a layer of semiconductor material glued on a support wafer  
A method of manufacturing a semiconductor device which starts with a semiconductor wafer (1) which is provided with a layer of semiconductor material (4) lying on an insulating layer (3) at a first...
6091131 Integrated circuit having crack stop for interlevel dielectric layers  
The propagation of a crack from the surface of the dielectric layer of an integrated circuit, through to the underlying circuit elements, is prevented by controlling the interface between the...
6037651 Semiconductor device with multi-level structured insulator and fabrication method thereof  
A semiconductor device with a multi-level insulator formed on a semiconductor substrate is provided, which enables to restraint of impurity atoms doped into a material contacted with the insulator...
6018184 Semiconductor structure useful in a self-aligned contact having multiple insulation layers of non-uniform thickness  
A semiconductor processing method is provided for making contact openings. It includes depositing several insulative layers and performing an anisotropic etch. One layer is a conformal oxide...
5994762 Semiconductor integrated circuit device including boron-doped phospho silicate glass layer and manufacturing method thereof  
A semiconductor integrated circuit device is provided in which an interlayer insulation film deposited on a semiconductor chip includes a boron-containing silicon oxide film and a second film...
5990555 Electronic circuit device with multi-layer wiring  
An electronic circuit having: a substrate with an upper surface; a lower level wiring made of conductive material and disposed on the substrate; an insulating cover film covering the surface of the...
5969409 Combined in-situ high density plasma enhanced chemical vapor deposition (HDPCVD) and chemical mechanical polishing (CMP) process to form an intermetal dielectric layer with a stopper layer embedded therein  
A wafer planarization process which utilizes combined high density plasma chemical vapor deposition (HDP-CVD) process and chemical mechanical polishing (CMP) process is disclosed. This process...
5936308 Interlocking conductive plug for use with an integrated circuit  
A method for forming an integrated circuit comprising providing a substrate comprising a node to which electrical connection is to be made; providing a layer of material outwardly of the node; and...
5925908 Integrated circuit including a non-volatile memory device and a semiconductor device  
An integrated circuit (10) is formed on a semiconductor substrate (20) and includes a non-volatile memory device (12) and a semiconductor device (11). The non-volatile memory device (12) includes a...
5907182 Semiconductor device having element with high breakdown voltage  
A semiconductor device which contains an electrode or an interconnection subjected to a high voltage prevents current leakage due to polarization of a mold resin. In this semiconductor device, a...
5905298 Semiconductor device having an insulation film of low permittivity and a fabrication process thereof  
An insulation structure is formed in a high-density plasma environment by depositing a first SiO 2 film containing a substantial amount of F without a substrate bias, followed by depositing a...
5877541 Contact structure for improving photoresist adhesion on a dielectric layer  
A method is provided for improving the adhesion between a photoresist layer and a dielectric, and an integrated circuit formed according to the same. A conformal dielectric layer is formed over the...
5872390 Fuse window with controlled fuse oxide thickness  
A fuse window structure and method for forming the same for a semiconductor device with a fuse and a cutting site on the fuse, the structure having (1) a first oxide region substantially in...
5864172 Low dielectric constant insulation layer for integrated circuit structure and method of making same  
A low dielectric insulation layer for an integrated circuit structure material, and a method of making same, are disclosed. The low dielectric constant insulation layer comprises a porous...
5821582 Structures for preventing reverse engineering of integrated circuits  
Embodiments according to the present invention provide tamper resistant structures which make it more difficult to reverse engineer integrated circuits. In one embodiment, a tamper resistant...
5811872 Semiconductor device and method of farbricating the same  
A semiconductor device includes an interlevel film constituted by a first dielectrics film containing dangling bonds and a bonded group of Si and hydrogen, and a second dielectrics film formed on...
5793110 MOS transistor with good hot carrier resistance and low interface state density  
After a MOS transistor having a gate electrode layer is formed on the surface of a semiconductor substrate, a first interlayer insulating film and a moisture blocking film are sequentially formed....
5739579 Method for forming interconnections for semiconductor fabrication and semiconductor device having such interconnections  
A method for forming interconnections for semiconductor fabrication and semiconductor devices have such interconnections are described. A first patterned dielectric layer is formed over a...
5723909 Semiconductor device and associated fabrication method  
A first metallization layer is locally formed on the surface of a semiconductor substrate thereby leaving portions of the semiconductor substrate's surface exposed. A first silicon oxide layer is...
5717233 Semiconductor device having capacitior and manufacturing method thereof  
A semiconductor device comprising an integrated circuit and a capacitor. In this capacitor, a bottom electrode, a dielectric film and a top electrode are formed, independently of the integrated...
5710462 Semiconductor integrated circuit device having multi-level wiring structure without dot pattern  
First plugs project from a lower inter-level insulating layer so as to be coplanar with an upper surface of a middle-level wiring on the lower-level insulating layer, and through-holes are formed...
5703404 Semiconductor device comprising an SiOF insulative film  
A semiconductor device having an interlayer insulating film improved to decrease film shrinkage and film stress is provided. Metal interconnections are formed on a substrate. A silicon oxide film...
5661344 Porous dielectric material with a passivation layer for electronics applications  
A semiconductor device and process for making the same are disclosed which use porous dielectric materials to reduce capacitance between conductors, while allowing conventional photolithography and...
5656852 High-dielectric-constant material electrodes comprising sidewall spacers  
Generally, the present invention utilizes a lower electrode comprising a sidewall spacer to fore a top surface with rounded comers on which HDC material can be deposited without substantial...
5646440 Interlayer dielectric structure for semiconductor device  
A semiconductor device having a base or main body on which conductive interconnects are formed. At least the surface of the base is insulative. A first dielectric film is formed so as to cover the...
5619064 III-V semiconductor gate structure and method of manufacture  
A manufacturable III-V semiconductor gate structure having small geometries is fabricated. A silicon nitride layer is formed on a III-V semiconductor material and a dielectric layer comprised of...
5619063 Edgeless, self-aligned, differential oxidation enhanced and difusion-controlled minimum-geometry antifuse and method of fabrication  
The present invention is directed to an antifuse structure and fabrication process wherein the bottom oxide of the ONO antifuse material layer is grown over a small area of N- diffusion surrounded...
5616960 Multilayered interconnection substrate having a resin wall formed on side surfaces of a contact hole  
A multilayered interconnection substrate which prevents contact failure from occurring and a process for fabricating the same, said multilayered interconnection substrate comprising a first...
5598028 Highly-planar interlayer dielectric thin films in integrated circuits  
A planarization process for the manufacturing of highly-planar interlayer dielectric thin films in integrated circuits, particularly in non-volatile semiconductor memory devices, comprises the...
5585653 Solid-state photoelectric imaging device with reduced smearing  
A solid-state imaging device which restrains the smear phenomenon effectively without reduction of the dielectric breakdown strength between the transfer electrode and the light shielding film. A...
5561318 Porous composites as a low dielectric constant material for electronics applications  
This invention provides a process for making a semiconductor device with reduced capacitance between adjacent conductors. This process can include applying and gelling one or more solutions between...
5554884 Multilevel metallization process for use in fabricating microelectronic devices  
A multilevel metallization is deposited on a microelectronic device base structure (40). The process includes depositing a glassy dielectric layer (48) of a thickness that is from about two to...
5541445 High performance passivation for semiconductor devices  
A method of passivating a semiconductor device, comprises depositing a first dielectric passivation layer on the surface of the device, forming at least one planarization layer over the first...
5525831 Semiconductor device with thin film resistor having reduced film thickness sensitivity during trimming process  
A thin film resistor on a semiconductor device may be laser trimmed while reducing the influence of film thickness of a passivation film formed on the thin film resistor. An underlying oxide film...
5523616 Semiconductor device having laminated tight and coarse insulating layers  
In a semiconductor device having a passivation layer, the passivation layer includes a laminated configuration formed by a plurality of tight insulating layers and a plurality of coarse insulating...
5523595 Semiconductor device having a transistor, a ferroelectric capacitor and a hydrogen barrier film  
A semiconductor device having a ferroelectric film or a polycrystalline silicon gate, a humidity-resistant hydrogen barrier film, like TiN film, TiON film, etc., formed by hydrogen non-emission...
Matches 101 - 150 out of 234 < 1 2 3 4 5 >