Matches 51 - 100 out of 234 < 1 2 3 4 5 >
Match Document Document Title
6913814 Lamination process and structure of high layout density substrate  
A lamination process and structure of a high layout density substrate is disclosed. The lamination process comprises the following steps. First of all, a plurality of laminating layers are...
6911686 Semiconductor memory device having planarized upper surface and a SiON moisture barrier  
There is provided a semiconductor device which is manufactured via steps of forming a capacitor which is obtained by forming in sequence an upper electrode, a dielectric film formed of...
6903445 Semiconductor device having low-K insulating film  
Disclosed is a semiconductor device having a dielectric film of a stacked structure, comprising a low dielectric constant film containing silicon, oxygen and carbon a modified layer for the low...
6894369 Semiconductor device having a high-dielectric gate insulation film and fabrication process thereof  
An ultra high-speed semiconductor device has a high-K dielectric gate insulator layer, wherein spread of impurities to a Si substrate from a gate electrode through the high-K dielectric gate...
6870225 Transistor structure with thick recessed source/drain structures and fabrication process of same  
An improved transistor structure that decreases source/drain (S/D) resistance without increasing gate-to-S/D capacitance, thereby increasing device operation. S/D structures are formed into...
6864562 Semiconductor device having active element connected to an electrode metal pad via a barrier metal layer and interlayer insulating film  
A semiconductor device of the present invention has (1) an active element provided on a semiconductor substrate, (2) an interlayer insulating film formed so as to cover the active element, (3) a...
6858937 Backend metallization method and device obtained therefrom  
A semiconductor device and a method of making it are described. During the formation of the semiconductor device, a hard mask is formed of an etch-resistant material. The mask prevents etchant from...
6853054 High frequency semiconductor device  
A high frequency semiconductor device including wiring layers which are formed above a semiconductor substrate and in which transmission lines are formed by combining with a ground plate having a...
6798057 Thin stacked ball-grid array package  
A thin-stacked ball grid array (BGA) package is created by coupling a semi-conducting die to each of the opposing faces of an interposer having bond pads and circuitry on both faces. Solder balls...
6798043 Structure and method for isolating porous low-k dielectric films  
A film structure includes low-k dielectric films and N—H base source films such as barrier layer films, etch-stop films and hardmask films. Interposed between the low-k dielectric film and...
6787886 Semiconductor device and methods of fabricating the same  
A semiconductor device includes a semiconductor substrate which has a major surface and a MOS transistor which has a gate and first and second diffusion regions and which is formed on the major...
6781216 Semiconductor device having wiring patterns with insulating layer  
A semiconductor device includes a semiconductor substrate having a center area where an IC is formed and a peripheral area surrounding the center area, a first wiring pattern formed on the...
6765283 Semiconductor device with multi-layer interlayer dielectric film  
A semiconductor device comprising: an underlayer interconnect layer; an interlayer dielectric film formed with a connection hole reaching the underlayer interconnect layer; and an upper...
6756672 Use of sic for preventing copper contamination of low-k dielectric layers  
A semiconductor device includes a first metallization level, a first diffusion barrier layer, a first etch stop layer, a dielectric layer and a via extending through the dielectric layer, the first...
6756635 Semiconductor substrate including multiple nitrided gate insulating films  
A silicon oxide film with a film thickness of 5 to 7 nm is formed on a first region, a silicon oxynitride film with a film thickness of 2 to 3 nm, and a nitrogen concentration of 1 to 3 atom % is...
6753568 Memory device  
A memory device includes a memory node ( 1 ) to which charge is written through a tunnel barrier configuration ( 2 ) from a control electrode ( 9 ). The stored charge effects the conductivity of a...
6734036 Semiconductor device and method of fabrication  
The invention is a semiconductor device and method of fabricating the device. The device includes a semiconductor substrate with an active region, and a low dielectric constant insulating layer...
6713847 Method of fabricating semiconductor device, and semiconductor device  
Wiring of the Dual-Damascene structure is formed without using the CMP method. As shown in FIG. 1 A, oxygen ions are implanted from an upper surface under the condition that the oxygen ions reach...
6713846 Multilayer high &kgr dielectric films  
A new multilayer dielectric film for improving dielectric constant and thermal stability of gate dielectrics is provided. The multilayer dielectric film comprises a first layer formed of a metal...
6710422 Semiconductor device and method of manufacturing the same  
A semiconductor device having conductive plug for connecting capacitor and conductive pattern, comprises first and second impurity diffusion regions formed in a semiconductor substrate, a first...
6686645 Fuse and fuse window structure  
A fuse structure. A first dielectric layer is formed on a substrate, a first conductive layer is formed on part of the first dielectric layer, a second dielectric layer is formed on part of the...
6670710 Semiconductor device having multi-layered wiring  
A semiconductor device is provided with a first insulating film, a first wiring layer formed in the first insulating film, a second insulating film formed above the first wiring layer and the first...
6664612 Semiconductor component having double passivating layers formed of two passivating layers of different dielectric materials  
A semiconductor component with passivation includes at least two double passivating layers, of which an uppermost is applied to a planar surface of a layer located therebelow. The double...
6657283 Reducing relative stress between HDP layer and passivation layer  
Structures for reducing relative stress between HDP layer and passivation layer are proposed by the invention, where the HDP layer is formed by high density plasma and the passivation layer is a...
6653718 Dielectric films for narrow gap-fill applications  
A colloidal suspension of nanoparticles composed of a dense material dispersed in a solvent is used in forming a gap-filling dielectric material with low thermal shrinkage. The dielectric material...
6623985 Structure of and manufacturing method for semiconductor device employing ferroelectric substance  
A semiconductor device and method for manufacturing the same in which the semiconductor device includes a substrate; an MOS transistor formed on the substrate; an interlayer dielectric provided on...
6614096 Method for manufacturing a semiconductor device and a semiconductor device  
Disclosed is a method for manufacturing a semiconductor device, which comprises the steps of forming a first insulating film made of a low dielectric constant material and containing carbon,...
6600228 Keyhole at the top metal level prefilled with photoresist to prevent passivation damage even for a severe top metal rule  
A planarized surface of a photoresist layer is formed above a layer formed over a hole in a blanket, conformal, silicon nitride layer which in turn is formed above a keyhole in metallization with...
6597042 Contact with germanium layer  
A contact to a semiconductor substrate including a contact opening extending through an insulating layer to a doped active region of the semiconductor substrate. The contact opening can have a...
6580155 Semiconductor device  
The semiconductor device comprising a lower conductive layer ( 11 ) and an upper conductive layer ( 12 ) which are formed via an interlayer insulator ( 20 ) on a substrate ( 1 ), wherein the...
6559052 Deposition of amorphous silicon films by high density plasma HDP-CVD at low temperatures  
Method and apparatus for depositing an amorphous silicon film on a substrate using a high density plasma chemical vapor deposition (HDP-CVD) technique is provided. The method generally comprises...
6555865 Nonvolatile semiconductor memory device with a multi-layer sidewall spacer structure and method for manufacturing the same  
The present invention provides a nonvolatile memory device having high reliability with novel sidewall spacer structures. The gate stack structure for use in a nonvolatile memory device comprises a...
6541863 Semiconductor device having a reduced signal processing time and a method of fabricating the same  
There is provided a semiconductor device comprising an insulating layer which is partly formed of porous material, and a method for fabricating the device. A stray capacitance of adjacent wiring...
6509601 Semiconductor memory device having capacitor protection layer and method for manufacturing the same  
A semiconductor memory device having a capacitor protection layer and a method for manufacturing the same. A capacitor of the semiconductor memory device is entirely covered with an encapsulating...
6504234 Semiconductor device with interlayer film comprising a diffusion prevention layer to keep metal impurities from invading the underlying semiconductor substrate  
An interlayer film covering a semiconductor device formed on the semiconductor substrate has a film having ability of gettering the metal impurities invading from an upper portion of the interlayer...
6486506 Flash memory with less susceptibility to charge gain and charge loss  
An integrated circuit is designed to reduce charge gain and charge loss in a flash memory or flash programmable read-only memory. Charge gain and loss caused by moisture or hydrogen diffusion or...
6469390 Device comprising thermally stable, low dielectric constant material  
It has been discovered that for semiconductor devices such as MOSFETs, there is significant capacitive coupling in the front-end structure, i.e., the structure from and including the device...
6462402 Microelectronic substrate comprised of etch stop layer, stiffening layer, and endpointing layer  
A method and apparatus for endpointing a planarization process of a microelectronic substrate. In one embodiment, the microelectronic substrate can include a semiconductor base, a first material,...
6445072 Deliberate void in innerlayer dielectric gapfill to reduce dielectric constant  
One aspect of the present invention relates to a method of forming an innerlayer dielectric, involving the steps of providing a substrate having at least two metal lines thereon; providing a...
6426546 Reducing relative stress between HDP layer and passivation layer  
Structures for reducing relative stress between HDP layer and passivation layer are proposed by the invention, where the HDP layer is formed by high density plasma and the passivation layer is a...
6414375 Semiconductor device with metal silicide film on partial area of substrate surface and its manufacture method  
First and second regions are defined in a principal surface of a semiconductor substrate. Two projected structures are disposed on the principal surface of the first region and spaced apart by a...
6388310 Semiconductor device with a passivation film  
The invention provides a semiconductor device with a passivation film provided on a surface thereof, said passivation film comprising a SiON layer in contact with the surface of said semiconductor...
6388337 Post-processing a completed semiconductor device  
A technique for post-processing a conventionally completed semiconductor device having a final passivation layer and bond pads exposed through the final passivation layer. The technique includes...
6384483 Manufacturing method for semiconductor device  
A manufacturing method for a semiconductor device, wherein a polyimide-based resin layer is covered with a P-CVD oxide silicon film or the like before it is subjected to degassing process in order...
6380610 Dislocation free local oxidation of silicon with suppression of narrow space field oxide thinning effect  
A novel design of an oxidation mask for improved control of birds beak and more specifically for tailoring and smoothing the field oxide isolation profile in the vicinity of the birds beak. The...
6376899 Planar guard ring  
An integrated circuit is provided. The integrated circuit includes a substrate and at least one dielectric layer and a metal layer formed upon the substrate. The at least one dielectric layer...
6333519 Semiconductor apparatus process for production thereof and liquid crystal apparatus  
A semiconductor apparatus of the type includes a plurality of semiconductor devices arranged in a matrix and each having a principal electrode, an insulating layer coating the semiconductor...
6320246 Semiconductor wafer assemblies  
The invention includes a semiconductor wafer assembly, comprising: a) a semiconductor wafer substrate; and b) alternating first and second layers over the semiconductor wafer substrate, the...
6320240 Semiconductor device and method of manufacturing the same  
There are provided a semiconductor device which can prevent short-circuit of the contact plugs and prevent exposure of wirings to ensure sufficient reliability even if level difference is caused in...
6303959 Semiconductor device having reduced source leakage during source erase  
In one aspect, the current invention provides a method for reducing the source leakage of a semiconductor device. The method comprises the steps of stacked gate etch, thin oxide formation, SAS...
Matches 51 - 100 out of 234 < 1 2 3 4 5 >