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7615491 Defectivity and process control of electroless deposition in microelectronics applications  
Methods and compositions for electrolessly depositing Co, Ni, or alloys thereof onto a substrate in manufacture of microelectronic devices. Grain refiners, levelers, oxygen scavengers, and...
7612453 Semiconductor device having an interconnect structure and a reinforcing insulating film  
A semiconductor device includes in an interconnect structure which includes a first interconnect made of a copper-containing metal, a first Cu silicide layer covering the upper portion of the first...
7611988 Defectivity and process control of electroless deposition in microelectronics applications  
Methods and compositions for electrolessly depositing Co, Ni, or alloys thereof onto a substrate in manufacture of microelectronic devices. Grain refiners, levelers, oxygen scavengers, and...
7611987 Defectivity and process control of electroless deposition in microelectronics applications  
Methods and compositions for electrolessly depositing Co, Ni, or alloys thereof onto a substrate in manufacture of microelectronic devices. Grain refiners, levelers, oxygen scavengers, and...
7589398 Embedded metal features structure  
A method and structure for creating embedded metal features includes embedded trace substrates wherein bias and signal traces are embedded in a first surface of the embedded trace substrate and...
7564100 Silicon on sapphire wafer  
The present invention provides an SOS wafer comprising a non-transparent polysilicon layer provided on a back surface of a sapphire substrate, a silicon nitride layer which protects the polysilicon...
7545004 Method and structure for forming strained devices  
A method for manufacturing a device includes mapping extreme vertical boundary conditions of a mask layer based on vertical edges of a deposited first layer and a second layer. The mask layer is...
7544607 Semiconductor device having thin film formed by atomic layer deposition and method for fabricating the same  
A semiconductor device having a thin film formed by atomic layer deposition and a method for fabricating the same, wherein the semiconductor device includes a liner layer formed on an internal wall...
7531891 Semiconductor device  
A semiconductor device having improved adhesiveness between films composing an interlayer insulating film is presented by providing multilayered films in the interlayer insulating films having film...
7525174 ***WITHDRAWN PATENT AS PER THE LATEST USPTO WITHDRAWN LIST***
High performance system-on-chip using post passivation process  
The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a...
7501691 Trench insulation structures including an oxide liner and oxidation barrier  
A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a liner layer preferably is deposited...
7492001 High K stack for non-volatile memory  
A memory device may include a source region and a drain region formed in a substrate and a channel region formed in the substrate between the source and drain regions. The memory device may further...
7489020 Semiconductor wafer assemblies  
An elevated containment structure in the shape of a wafer edge ring surrounding a surface of a semiconductor wafer is disclosed, as well as methods of forming and using such a structure. In one...
7485949 Semiconductor device  
A semiconductor device is disclosed. The device includes a substrate, a first porous SiCOH dielectric layer, a second porous SiCOH dielectric layer, and an oxide layer. The first porous SiCOH...
7482627 Semiconductor device, and method of fabricating the same  
A crystalline semiconductor film in which the locations and sizes of crystal grains have been controlled, is prepared, and a TFT capable of high speed operation is realized by employing the...
7436009 Via structures and trench structures and dual damascene structures  
Via hole and trench structures and fabrication methods are disclosed. The structure includes a conductive layer in a dielectric layer, and a via structure in the dielectric layer contacting a...
7425763 Electronic circuit package  
An electronic apparatus which includes a wiring substrate which includes wiring conductors, and a plurality of semiconductor bare chips that are formed on the wiring substrate. The semiconductor...
7422927 Methods of forming a resistance variable element  
The invention includes methods of depositing silver onto a metal selenide-comprising surface, and methods of forming a resistance variable device. In one implementation, a method of depositing...
7410899 Defectivity and process control of electroless deposition in microelectronics applications  
Methods and compositions for electrolessly depositing Co, Ni, or alloys thereof onto a substrate in manufacture of microelectronic devices. Grain refiners, levelers, oxygen scavengers, and...
7405466 Method of fabricating microelectromechanical system structures  
A method of simultaneously bonding components, comprising the following steps. At least first, second and third components are provided and comprise: at least one glass component; and at least one...
7397073 Barrier dielectric stack for seam protection  
The present invention provides a semiconducting device including a gate dielectric atop a semiconducting substrate, the semiconducting substrate containing source and drain regions adjacent the...
7396777 Method of fabricating high-k dielectric layer having reduced impurity  
Methods of fabricating high-k dielectric layers having reduced impurities for use in semiconductor applications are disclosed. The methods include the steps of: forming a stacked dielectric layer...
7396718 Technique for creating different mechanical strain in different channel regions by forming an etch stop layer stack having differently modified intrinsic stress  
A technique is provided that allows the formation of contact etch stop layers having different intrinsic stress for different transistors, while substantially avoiding any device degradation owing...
7391116 Fretting and whisker resistant coating system and method  
A coated electrically conductive substrate has particular utility where there are multiple closely spaced leads and tin whiskers constitute a potential short circuit. This electrically conductive...
7391094 Semiconductor structure and method of making same  
A semiconductor structure includes a substrate having a surface and being made of a material that provides atypical surface properties to the surface, a bonding layer on the surface of the...
7368804 Method and apparatus of stress relief in semiconductor structures  
A method, apparatus and system are provided for relieving stress in the via structures of semiconductor structures whenever a linewidth below a via is larger than a ground-rule, including providing...
7358587 Semiconductor structures  
In one aspect, the invention includes a method of forming a material within an opening, comprising: a) forming an etch-stop layer over a substrate, the etch-stop layer having an opening extending...
7355268 High reflector tunable stress coating, such as for a MEMS mirror  
An optical device having a high reflector tunable stress coating includes a micro-electromechanical system (MEMS) platform, a mirror disposed on the MEMS platform, and a multiple layer coating...
7352053 Insulating layer having decreased dielectric constant and increased hardness  
A method of manufacturing a mechanically robust insulating layer, including forming a low-k dielectric layer having a first dielectric constant on a substrate and forming a carbon nitride cap layer...
7332796 Devices and methods of preventing plasma charging damage in semiconductor devices  
Methods for protecting semiconductor devices from plasma charging damage are disclosed. An example disclosed method includes depositing an etching stop layer on a substrate with at least one...
7332795 Dielectric passivation for semiconductor devices  
A semiconductor device is disclosed that includes a layer of Group III nitride semiconductor material that includes at least one surface, a control contact on the surface for controlling the...
7317241 Semiconductor apparatus having a large-size bus connection  
In a semiconductor apparatus of the present invention, a plurality of circuit components are provided. A first bus interconnects the circuit components. A second bus interconnects the circuit...
7287320 Method for programming a routing layout design through one via layer  
A method for programming a routing layout design through one via layer includes forming a plurality of metal traces on a first routing layer and a second routing layer, and positioning a plurality...
7285826 High mobility CMOS circuits  
Semiconductor structure formed on a substrate and process of forming the semiconductor. The semiconductor includes a plurality of field effect transistors having a first portion of field effect...
7253472 Method of fabricating semiconductor device employing selectivity poly deposition  
A method for fabricating a semiconductor device employing a selectivity poly deposition is disclosed. The disclosed method comprises depositing selectivity poly on a gate poly and source/drain...
7235865 Methods for making nearly planar dielectric films in integrated circuits  
In the fabrication of integrated circuits, one specific technique for making surfaces flat is chemical-mechanical planarization. However, this technique is quite time consuming and expensive,...
7235469 Semiconductor device and method for manufacturing the same  
A semiconductor device suitable for the miniaturization and comprising properly controlled Si/SiGe gate electrode comprises an insulator formed on a semiconductor substrate, a first gate electrode...
7227244 Integrated low k dielectrics and etch stops  
A method of depositing and etching dielectric layers having low dielectric constants and etch rates that vary by at least 3:1 for formation of horizontal interconnects. The amount of carbon or...
7217989 Composition for selectively polishing silicon nitride layer and polishing method employing it  
To provide a polishing composition whereby the stock removal rate of a silicon nitride layer is higher than the stock removal rate of a silicon oxide layer, there is substantially no adverse effect...
7214629 Strain-silicon CMOS with dual-stressed film  
A semiconductor device has an NMOS portion and a PMOS portion. A first stress layer overlies a first channel to provide a first stress type to the channel and a first modified stress layer is...
7211869 Increasing carrier mobility in NFET and PFET transistors on a common wafer  
Enhanced carrier mobility in transistors of differing (e.g. complementary) conductivity types is achieved on a common chip by provision of two or more respective stressed layers, such as etch stop...
7208836 Integrated circuitry and a semiconductor processing method of forming a series of conductive lines  
A semiconductor processing method of forming a plurality of conductive lines includes, a) providing a substrate; b) providing a first conductive material layer over the substrate; c) providing a...
7205662 Dielectric barrier layer films  
In accordance with the present invention, a dielectric barrier layer is presented. A barrier layer according to the present invention includes a densified amorphous dielectric layer deposited on a...
7205652 Electronic assembly including multiple substrates  
An electronic assembly includes a first substrate and a second substrate. The first substrate includes a first surface having a first plurality of conductive traces formed on an electrically...
7202546 Integrated circuit with copper interconnect and top level bonding/interconnect layer  
An integrated circuit including a copper interconnection layer includes an aluminum distribution layer overlying the copper interconnection layer to distribute external electrical signals such as...
7199448 Integrated circuit configuration comprising a sheet-like substrate  
An integrated circuit is formed on a non-planar substrate. The integrated circuit is formed over a plurality of layers. Chemical or physical changes in the microstructure of the substrate cause the...
7195966 Methods of fabricating semiconductor devices including polysilicon resistors and related devices  
Methods of fabricating semiconductor devices are provided. Transistors are provided on a semiconductor substrate. A first interlayer insulating layer is provided on the transistors. A second...
7190033 CMOS device and method of manufacture  
A CMOS device and manufacturing method thereof wherein a bilayer etch stop is used over a PMOS transistor, and a single etch stop layer is used for an NMOS transistor, for forming contacts to the...
7138703 Preventive film for polarizer and polarizing plate using the same  
A preventive film for a polarizer which comprises a non-oriented two-layer film comprising a polycarbonate film having a glass transition temperature of 100° C. or higher and, laminated on one...
7138290 Methods of depositing silver onto a metal selenide-comprising surface and methods of depositing silver onto a selenium-comprising surface  
The invention includes methods of depositing silver onto a metal selenide-comprising surface, and methods of forming a resistance variable device. In one implementation, a method of depositing...
Matches 1 - 50 out of 315 1 2 3 4 5 6 7 >