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5969384 |
Flash memory having separate data programming and erasing terminals
A method of fabricating a flash memory having a vertical floating gate terminal layer and controlling gate terminal layer structure, which is suitable for use in ultra-high density IC circuits, and...
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5960020 |
Semiconductor laser diode including ridge and partially disordered active layer
A ridge type laser diode with a stabilized horizontal transverse mode and little variation in peak output power and a method for producing the laser. The ridge type laser diode includes a...
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5956568 |
Methods of fabricating and contacting ultra-small semiconductor devices
A method of fabricating ultra-small semiconductor devices including providing a mesa on a substrate. A plurality of overlying layers of semiconductor material are grown in overlying relationship to...
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5943591 |
Integrated circuit scribe line structures and methods for making same
A method for forming a scribe line on a semiconductor wafer including the steps of: (a) providing a semiconductor substrate; and (b) sequentially providing a plurality of layers over the...
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5939738 |
Low base-resistance bipolar transistor
A method for fabricating a bipolar transistor comprising the steps of: implanting portions 320 of a semiconductor material structure with ions to render the portions semi-insulating; forming an...
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5929498 |
Fusion-bond electrical feed-through
A semiconductor device has a flexible structure bonded to a semiconductor substructure to form a cavity. The flexible structure is bonded over a conducting feed-through without the feed-through...
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5930653 |
Method of manufacturing a semiconductor device for surface mounting suitable for comparatively high voltages, and such a semiconductor device
The invention relates to a method of manufacturing a semiconductor device whereby an upper side of a wafer of semiconductor material (12) is provided with semiconductor elements in passivated mesa...
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5920102 |
Semiconductor device having a decoupling capacitor and method of making
A semiconductor device (10) is formed in a pedestal structure (16) overlying an epitaxial layer (12) and a semiconductor substrate (11). The semiconductor device (10) includes a doped region (13)...
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5920773 |
Method for making integrated heterojunction bipolar/high electron mobility transistor
An integrated circuit technology combines heterojunction bipolar transistors (HBTs), high electron mobility transistors (HEMTs) and other components along with interconnect metallization on a...
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5914527 |
Semiconductor device
The present invention is directed to a semiconductor device and method wherein a vertical opening is provided or formed completely through a semiconductor substrate of the semiconductor device to...
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5907165 |
INP heterostructure devices
The specification describes a metal contact material optimized for diffused contacts to the buried emitter-base junction in DHBT devices. The metal contact material is a multilayer structure of...
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5886389 |
Field-effect transistor and method for producing the same
A field-effect transistor includes a semiconductor substrate including a source region, a drain region and a channel region located between the source and drain regions; a gate insulating film...
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5880499 |
Memory cell of a nonvolatile semiconductor device
A non-volatile semiconductor memory device formed on a semiconductor substrate of a first conductivity type. The semiconductor memory including a plurality of recessed portions formed on a surface...
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5844250 |
Field emission element with single crystalline or preferred oriented polycrystalline emitter or insulating layer
A process for manufacturing a field emission element including a substrate, and an emitter and a gate each arranged on the substrate is provided. The emitter is formed at at least a tip portion...
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5834812 |
Edge stripped BESOI wafer
A process for stripping the outer edge of a bonded BESOI wafer. The bonded BESOI wafer comprises a handle wafer, an oxide layer on one surface of the handle wafer, a device layer bonded to the...
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5834810 |
Asymmetrical vertical lightly doped drain transistor and method of forming the same
An asymmetrical vertical lightly doped drain metal oxide semiconductor field effect transistor (VLDD MOSFET) is formed on a semiconductor substrate. The substrate includes first and second main...
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5825050 |
Thin film transistor having tapered active layer formed by controlling defect density and process of fabrication thereof
Defect density of amorphous silicon layers is increased from the lowest layer toward the highest layer by controlling one of or both of the pressure of gaseous mixture containing silane and...
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5814531 |
Method for forming semiconductor laser emitting light from slant plane
A semiconductor laser includes a patterned semiconductor substrate including a lower flat plane portion, an upper flat plane portion, and a stripe-shaped slant plane portion connecting the lower...
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5814861 |
Symmetrical vertical lightly doped drain transistor and method of forming the same
A symmetrical vertical lightly doped drain metal oxide semiconductor field effect transistor (VLDD MOSFET) is formed on a semiconductor substrate. The substrate includes a first region having a...
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5804846 |
Process for forming a self-aligned raised source/drain MOS device and device therefrom
The present invention is directed to a process for forming a self-aligned raised source/drain MOS device comprising a planarized metal layer, preferably tungsten, overlying a source, a drain, and a...
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5801427 |
Semiconductor device having a polycide structure
In a semiconductor device having a polycide structure located on a stepped portion, halation during formation of a resist pattern is prevented, and oxidation of an upper surface of a...
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5796122 |
Method for planarizing wide bandgap semiconductor devices
A method of planarizing wide bandgap semiconductor devices selected from a group including SiC, GaN and diamond having a mesa defined thereon by a trench with a depth of 1 to 2 micrometers and a...
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5793055 |
Hybrid electronic devices, particularly Josephson transistors
A step junction is provided for superconductor/semiconductor heterostructure hybrid devices like tunneling transistors, in a body of p-InAs with a vertical side connecting the low plateau and high...
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5783856 |
Method for fabricating self-assembling microstructures
A method for assembling microstructures onto a substrate through fluid transport. The microstructures being shaped blocks self-align into recessed regions located on a substrate such that the...
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5773874 |
Semiconductor device having a mesa structure for surface voltage breakdown
A semiconductor device comprises a monocrystalline silicon wafer having a major surface lying in the <100> crystal plane. Disposed on the surface is a mesa having a generally square...
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5767540 |
Hetero-junction bipolar transistor having AlGaAsP emitter layer underneath a base electrode
A hetero-junction bipolar transistor comprising a collector layer, a base layer and an emitter layer formed stepwise in this order wherein the emitter layer comprises a plurality of layers...
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5760476 |
Interconnect run between a first point and a second point in a semiconductor device for reducing electromigration failure
In a first approach, an interconnect structure (10) reduces peak localized interconnect current density by distributing current flow around the perimeter (22) of an interlevel connector (14) in a...
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5747856 |
Vertical channel masked ROM memory cell with epitaxy
A device and a method of manufacture of a semiconductor device on a semiconductor substrate is provided. An N+ source layer is formed on the surface of the semiconductor substrate. A dielectric...
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5747831 |
SIC field-effect transistor array with ring type trenches and method of producing them
SiC field-effect transistors with source, gate and drain contacts and in which the source contacts are located on the surface of the semiconductor wafer, the drain contacts on the underside of the...
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5739574 |
SOI semiconductor device with low concentration of electric field around the mesa type silicon
A semiconductor device which includes a mesa type silicon film with a source/drain region and a channel region formed therein, a gate oxide film formed on the mesa type silicon film, and a gate...
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5719433 |
Semiconductor component with integrated heat sink
A semiconductor component that could be a power transistor type of component comprises mesa-structured elementary bipolar transistors. This component has a thick, metal heat sink of which a part...
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5672904 |
Schottky carrier diode with plasma treated layer
A Schottky barrier diode having improved breakdown characteristics has an n + semiconductor layer and an n - semiconductor layer provided on the n + semiconductor layer. The n - semiconductor...
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5668401 |
Chessboard pattern layout for scribe lines
A process has been developed in which photoresist thinning at the edges of silicon chips, resulting from photoresist flowing from semiconductor chips, exhibiting features with raised topographies,...
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5665999 |
Metal-semiconductor diode and process for preparing metal-semiconductor diodes
It is suggested for a metal-semiconductor diode that the depletion zone layer be grown epitaxially from deformed In x Ga 1 -x As with an indium content x increasing in the direction of the metal...
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5659179 |
Ultra-small semiconductor devices having patterned edge planar surfaces
Ultra-small semiconductor devices and a method of fabrication including patterning the planar surface of a substrate to form a pattern edge (e.g. a mesa) and consecutively forming a plurality of...
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5656842 |
Vertical mosfet including a back gate electrode
Semiconductor regions (2, 12) includes pillar-like projections (3, 13) extending vertically from major surfaces of the semiconductor regions and each having a vertical outer surface and an inner...
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5652436 |
Smooth diamond based mesa structures
A diamond-based structure includes a substrate, an adhesive material on a face of the substrate, and an array of spaced apart diamond mesas bonded to the substrate by the adhesive material. In...
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5640043 |
High voltage silicon diode with optimum placement of silicon-germanium layers
A high voltage silicon rectifier includes a substrate portion and an epitaxial mesa portion that is a frustrum of a pyramid with a substantially square cross section and side walls that make a...
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5625206 |
High-speed double-heterostructure bipolar transistor devices
The total base-collector capacitance of a double-heterostructure bipolar transistor device is reduced by removing semiconductor material from the extrinsic regions and replacing the removed...
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5610434 |
Mesa semiconductor structure
Mesa diodes of improved mechanical properties are formed by providing a central depression in the regions of the chip from which the mesa is formed before the diffusion step that forms the...
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5602420 |
Stacked high mounting density semiconductor devices
A semiconductor device is provided with a stack of a plurality of semiconductor elements each having a bump deposited on each of surface electrodes, and a plurality of leads disposed closely...
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5600161 |
Sub-micron diffusion area isolation with Si-SEG for a DRAM array
The present invention is a process for forming diffusion areas and field isolation regions on a silicon substrate, by the steps of: growing a field oxide layer on the surface of the substrate;...
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5598037 |
Semiconductor device with a contact member made of semiconductor material having a columnar structure
A semiconductor device including: an insulated gate type transistor having a columnar semiconductor region formed on the main side of a semiconductor substrate, a gate electrode formed on the side...
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5581116 |
Semiconductor device manufactured by selectively controlling growth of an epitaxial layer without a mask
A semiconductor structure including: a substrate having a step portion; a first semiconductor layer formed on a region of the substrate which is selectively irradiated by light at an angle with...
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5578843 |
Semiconductor sensor with a fusion bonded flexible structure
Fabrication of semiconductor devices with movable structures includes local oxidation of a wafer and oxide removal to form a depression in an elevated bonding surface. A second wafer is fusion...
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5554859 |
Electron emission element with schottky junction
This is an electron emission with a semiconductor substrate having a p-type semiconductor layer whose impurity concentration falls within a concentration range for causing an avalanche breakdown in...
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5550392 |
Semiconductor switching devices
A process for manufacturing a semiconductor switching device (such as a thyristor device) comprises: etching a face of a semiconductor body to provide islands and channels which define a...
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5548149 |
Varying the thickness of the surface silicon layer in a silicon-on-insulator substrate
A preferred embodiment of this invention is a silicon-on-insulator structure comprising a semiconductor substrate (e.g. Si 36), a buried insulator layer (e.g. SiO 2 34) overlaying the substrate,...
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5539229 |
MOSFET with raised STI isolation self-aligned to the gate stack
A semiconductor structure comprising a transistor having a gate conductor that has first and second edges bounded by raised isolation structures (e.g. STI). A source diffusion is self-aligned to...
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5528060 |
Microwave heterojunction bipolar transistors suitable for low-power, low-noise, and high-power applications
Generally, and in one form of the invention, a microwave heterojunction bipolar transistor suitable for low-power, low-noise and high-power applications having an emitter, a base 50 and a collector...
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