Matches 101 - 150 out of 491 < 1 2 3 4 5 6 7 8 9 10 >
Match Document Document Title
6538273 Ferroelectric transistor and method for fabricating it  
A ferroelectric transistor is disclosed which has two source/drain regions and a channel region disposed in between in a semiconductor substrate. A metallic intermediate layer is disposed on the...
6538301 Semiconductor device and method with improved flat surface  
A semiconductor substrate has an element formation region and a scribe line region surrounding the element formation region. A metal wiring layer is formed so as to cover end portions of a...
6525403 Semiconductor device having MIS field effect transistors or three-dimensional structure  
A semiconductor projection is formed on a semiconductor substrate of the first conductivity type and has a semiconductor layer of the first conductivity type. The semiconductor projection has a top...
6515348 Semiconductor device with FET MESA structure and vertical contact electrodes  
A semiconductor device comprises one or more field effect devices (FD) having source and drain regions ( 5 and 6 ) spaced apart by a body region ( 3 a ). A gate structure ( 7 a , 7 b ),...
6512275 Semiconductor integrated circuits  
A semiconductor apparatus and method for making the same is disclosed herein in which the semiconductor apparatus includes a first active device formed in a mesa region of semiconductor material...
6509626 Conductive device components of different base widths formed from a common conductive layer  
A microelectronic device fabricating method includes providing a substrate having a mean global outer surface extending along a plane. A first portion is formed over the substrate comprising a...
6472682 Optical modulator, semiconductor laser device equipped with an optical modulator, and optical communication system  
An optical modulator and a semiconductor laser device including the optical modulator, both reducing variations in the refractive index of an optical modulator or making variations negative without...
6462399 Multi-chip module employing a carrier substrate with micromachined alignment structures and method of forming  
A micromachined insulative carrier substrate preferably formed of silicon and a multi-chip module formed from the micromachined substrate. The micromachined substrate is fabricated by forming mesas...
6429042 Method of reducing shear stresses on IC chips and structure formed thereby  
A method and structure for reducing mechanical shear stresses induced in an IC chip by metal interconnect lines that interconnect the chip with its surrounding substrate. A dielectric layer...
6404027 High dielectric constant gate oxides for silicon-based devices  
A high dielectric rare earth oxide of the form Mn 2 O 3 (such as, for example, Gd 2 O 3 or Y 2 O 3 ) is grown on a clean silicon (100) substrate surface under an oxygen partial pressure less than...
6388334 System and method for circuit rebuilding via backside access  
A circuit modification tool and method for a flip-chip IC permits access to circuit regions near the interconnects using an aperture formed through the circuit side. In one embodiment, an etching...
6384439 DRAM memory cell and array having pass transistors with recessed channels  
A dynamic random access memory (DRAM) cell and associated array are disclosed. In a first embodiment, the DRAM cell ( 300 ) includes a storage capacitor ( 304 ) and a pass transistor ( 302 ). The...
6359290 Self-aligned bump bond infrared focal plane array architecture  
A method of making a diode and the diode wherein there is provided a substrate of p-type group II-VI semiconductor material and an electrically conductive material capable of forming an ohmic...
6351023 Semiconductor device having ultra-sharp P-N junction and method of manufacturing the same  
A semiconductor device such as a P-N or P-I-N junction diode, includes a first semiconductor layer having a first conductivity-type and being mounted over a metal address line, and a second...
6335559 Semiconductor device cleave initiation  
The present invention relates to a method of etching a semiconductor wafer ( 100 ), particularly of a compound semiconductor, in order to facilitate cleaving of devices ( 200 ) from the wafer ( 100...
6329702 High frequency carrier  
A high frequency carrier is provided which comprises: (a) a planar ceramic substrate having first and second faces and (b) at least one feed-through extending from the first face to the second...
6316833 Semiconductor device with multilayer interconnection having HSQ film with implanted fluorine and fluorine preventing liner  
A semiconductor device with a multilevel interconnection has hydrogen silsesquioxane films which are made porous by etching action of hydrogen fluoride or by ion-implantation of impurities...
6316796 Single crystal silicon sensor with high aspect ratio and curvilinear structures  
In one aspect, the invention provides a semiconductor sensor which includes a first single crystal silicon wafer layer. A single crystal silicon structure is formed in the first wafer layer. The...
6294841 Integrated semiconductor circuit having dummy structures  
An integrated semiconductor circuit includes dummy structures. A portion of capacitive elements present in the dummy structures is used in order to adapt input/output parameters of pads of the...
6294414 Method of fabricating heterointerface devices having diffused junctions  
This invention is predicated upon applicants'discovery that the quality of high performance heterointerface devices having diffused junction depends significantly on the rate of cooling after...
6288454 Semiconductor wafer having a layer-to-layer alignment mark and method for fabricating the same  
A method of creating a layer-to-layer alignment mark in a semiconductor wafer includes the step of depositing a first conductor layer on a substrate associated with the semiconductor wafer. The...
6268642 Wafer level package  
A wafer level package structure. The method of forming the wafer level package structure includes covering a silicon chip having a plurality of integrated circuit devices thereon with an insulation...
6265757 Forming attached features on a semiconductor substrate  
A method for creating attached features while controlling the depth profile between the features is presented. First the features are formed with a separating barrier between the features. The...
6248429 Metallized recess in a substrate  
The present invention relates to the formation of a ball grid array testing receiver that is scalable for design consideration of miniaturization. A dielectric layer is formed upon a substrate that...
6245653 Method of filling an opening in an insulating layer  
The present invention is about a method for filling an opening in an insulating layer in a fast and highly reliable way and can be used to fill openings such as trenches and via holes...
6236111 Hybrid circuit substrate mountable micro-electromechanical component  
A micro-electromechanical component (10) which includes a micro-system in a chip made by deposit, photolithography and micro-manufacturing of successive layers. The micro-system comprises a...
6208007 Buried layer in a semiconductor formed by bonding  
Buried layers are formed within a semiconductor. Metallic or insulating buried layers are produced several microns within a semiconductor substrate. The buried layer can confine current to the...
6208013 Microactuator with an improved semiconductor substrate and method of forming the same  
The present invention provides semiconductor substrate for a microactuator having at least a movable part and a stator, wherein the semiconductor substrate has a plurality of semiconductor tapered...
6198144 Passivation of sidewalls of a word line stack  
A method of fabricating an integrated circuit on a wafer includes forming a gate electrode stack over a gate dielectric and forming nitride spacers along sidewalls of the gate electrode stack other...
6198158 Memory circuit including a semiconductor structure having more usable substrate area  
A semiconductor structure includes a first substrate portion having a surface and a first active region disposed in the first substrate portion. An insulator region is disposed on the first...
6157060 High density integrated semiconductor memory and method for producing the memory  
The high density integrated semiconductor memory has an EPROM cell in the form of a pillar. The cell has a floating gate and a control gate. The EPROM cell is dimensioned so thin that it is fully...
6136667 Method for bonding two crystalline substrates together  
A process for device fabrication is disclosed in which two substrates having different crystal lattices are bound together. In the process the substrate surfaces are thoroughly cleaned and placed...
6127733 Check pattern for via-hole opening examination  
To provide a check pattern whereby whether via-hole openings are made correctly or not can be examined without needing high precision positioning of the via-holes, a check pattern of the invention...
6127717 Totally self-aligned transistor with polysilicon shallow trench isolation  
A totally self-aligned transistor with shallow trench isolation. A single mask is used to align the source, drain, gate and isolation areas. Overlay error is greatly reduced by the use of a single...
6121633 Latch-up free power MOS-bipolar transistor  
A MOS bipolar transistor is provide which includes a silicon carbide npn bipolar transistor formed on a bulk single crystal n-type silicon carbide substrate and having an n-type drift layer a...
6121651 Dram cell with three-sided-gate transfer device  
A DRAM device and a process of manufacturing the device. The DRAM device includes a bit-line coupled to a signal storage node through a transfer device that is controlled by a word line. The...
6100549 High breakdown voltage resurf HFET  
A high breakdown voltage HFET includes a reduced surface field (RESURF) layer of p-type conductivity GaN positioned on a substrate with a channel layer of n-type conductivity GaN positioned...
6091083 Gallium nitride type compound semiconductor light-emitting device having buffer layer with non-flat surface  
A gallium nitride type compound semiconductor light-emitting device of the present invention includes: a substrate; a buffer layer, formed on the substrate, having a thick region and a thin region...
6069390 Semiconductor integrated circuits with mesas  
A semiconductor apparatus and method for making the same is disclosed herein in which the semiconductor apparatus includes a first active device formed in a mesa region of semiconductor material...
6051871 Heterojunction bipolar transistor having improved heat dissipation  
A heterojunction bipolar transistor has a mesa including collector 604, base 603, and emitter 602 layers. The mesa has first and second sidewalls 606. An improved heat dissipation structure...
6051889 Semiconductor device having a flip-chip structure  
A semiconductor device includes a substrate having a first principal surface carrying thereon a first wiring pattern and a semiconductor chip having a second principal surface carrying a second...
6034332 Power supply distribution structure for integrated circuit chip modules  
A power distribution structure for a multichip module including, a base plate, a plurality of mesas arranged in a pattern are formed on the base plate, the mesas having electrically conductive...
6034416 Semiconductor device and method for fabricating the same  
The top surface of a substrate in a peripheral circuit region is at a level that is higher than the top surface of the substrate in a memory cell region and that is substantially equal to the top...
6028347 Semiconductor structures and packaging methods  
A semiconductor structure having: semiconductor devices formed in an inner region of a semiconductor chip; a seal ring formed in the chip and disposed about the inner region; and, a plurality of...
6022781 Method for fabricating a MOSFET with raised STI isolation self-aligned to the gate stack  
A semiconductor structure comprising a transistor having a gate conductor that has first and second edges bounded by raised isolation structures (e.g. STI). A source diffusion is self-aligned to...
6020603 Semiconductor device with a beveled and chamfered outer peripheral portion  
A high voltage semiconductor device such as a gate turn-off thyristor, reduces surface field concentration of a main P-N junction part and attains withstand voltage increase. In a semiconductor...
5994747 MOSFETs with recessed self-aligned silicide gradual S/D junction  
The present invention includes a gate oxide. A gate is formed on the gate oxide. Undercut portions, formed under the gate. The substrate has recessed portions are adjacent to the gate. A silicon...
5990519 Electrostatic discharge structure  
A spike electrostatic discharge (ESD) cavity structure includes an etching stop layer including, for example, polysilicon or metal material. The etching stop layer is used as the etching stop to...
5982023 Semiconductor device and field effect transistor  
A dummy gate is removed together with an SiO 2 film thereon by lift-off to form a reverse dummy-gate pattern with the SiO 2 film. A photoresist pattern is formed to cover the reverse dummy-gate...
5981975 On-chip alignment fiducials for surface emitting devices  
An optoelectronic apparatus has, a die having a mesa (103) with a surface emitting optical device and a metallized p-type contact (209), a planar pad (201) adjacent the mesa for Z-height...
Matches 101 - 150 out of 491 < 1 2 3 4 5 6 7 8 9 10 >