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6853051 |
Thin film capacitor and method of manufacturing the same
A thin film capacitor comprising an insulating substrate, a capacitor structure located on the substrate, the capacitor structure having a dielectric layer sandwiched between a lower electrode...
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6853063 |
Semiconductor device and communication terminal using thereof
Wire bonding or printed wiring board leads or, alternatively, lead frames or equivalents thereof are used to electrically connect external electrodes of high withstand voltage capacitors formed on...
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6853476 |
Charge control circuit for a micro-electromechanical device
A charge control circuit for controlling a micro-electromechanical device having a variable capacitance is disclosed. In one embodiment, a charge storage device is configured to store a charge...
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6853052 |
Semiconductor device having a buffer layer against stress
A semiconductor device and a method for preparing the same that can solve crack of a semiconductor film, capacitance electrodes and the like due to stress when forming a source electrode and a...
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6849920 |
Semiconductor capacitive element, method for manufacturing same and semiconductor device provided with same
A semiconductor capacitor configured so as to use buried wirings, as electrodes, formed in an interlayer dielectric is provided on a semiconductor substrate which is capable of preventing an...
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6849387 |
Method for integrating copper process and MIM capacitor for embedded DRAM
A method for integrating copper with an MIM capacitor during the formation the MIM capacitor. The MIM capacitor is generally formed upon a substrate and at least one copper layer is deposited upon...
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6845551 |
Method of making a power electronics capacitor
There is disclosed herein a high voltage and high temperature power electronics capacitor which comprises one or more insulator layers of mica paper, and one or more metal conductor layers, all...
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6838717 |
Stacked structure for parallel capacitors and method of fabrication
A monolithic integrated circuit including a capacitor structure. In one embodiment the integrated circuit includes at least first and second levels of interconnect conductor for connection to a...
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6838721 |
Integrated circuit with a transitor over an interconnect layer
An integrated circuit ( 101 ) includes electrical circuitry ( 105 ) formed on a substrate ( 103 ). An interconnect layer ( 109, 117 ) is formed over the electrical circuitry ( 105 ). In one...
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6836398 |
System and method of forming a passive layer by a CMP process
The present invention provides systems and methods that facilitate formation of semiconductor devices via planarization processes. The present invention utilizes dishing effects that typically...
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6835977 |
Variable capactor structure
A variable capacitor comprising a substrate having a first type ion-doped buried layer, a first type ion-doped well, a second type ion-doped region and a conductive layer thereon. The first type...
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6833605 |
Method of making a memory cell capacitor with Ta2O5 dielectric
The present invention provides a method for making an integrated circuit capacitor having a Ta 2 O 5 dielectric which includes a high-temperature nitrogen anneal and a low-temperature ozone anneal...
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6833578 |
Method and structure improving isolation between memory cell passing gate and capacitor
A memory cell comprising a capacitor having a dielectric layer interposing first and second vertically disposed electrodes, an insulating lining located over the capacitor, and a transistor gate...
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6825080 |
Method for forming a MIM capacitor
A method of manufacturing a MIM capacitor which is characterized as follows. We provide a semiconductor structure having a first region and a capacitor region. Next we form a first conductive layer...
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6825490 |
On chip resistor calibration structure and method
A structure and associated method to determine an actual resistance value of a calibration resistor within a semiconductor device. The semiconductor device comprises a capacitor, a calibration...
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6825545 |
On chip decap trench capacitor (DTC) for ultra high performance silicon on insulator (SOI) systems microprocessors
A semiconductor method integrates a DTC on SOI for the purpose of accomplishing a robust circuit design with low noise while reducing the silicon area used. The DTC for SOI devices comprises a...
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6822311 |
DC or AC electric field assisted anneal
A method for forming a desired junction profile in a semiconductor device. At least one dopant is introduced into a semiconductor substrate. The at least one dopant is diffused in the semiconductor...
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6822312 |
Interdigitated multilayer capacitor structure for deep sub-micron CMOS
A capacitor structure having a first level of electrically conductive parallel lines and at least a second level of electrically conductive parallel lines disposed over the lines in the first...
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6818498 |
Capacitance element and method of manufacturing the same
On a substrate, there are provided a lower electrode, a capacitance insulating film, a passivation insulating film, and a first partial film of an upper electrode to be filled in a second aperture...
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6815796 |
Composite module and process of producing same
A composite module and its production process which allow multiple functions, miniaturization, low power consumption and low costs without requiring any external chip parts at all. A high-frequency...
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6815798 |
Integrated capacitor for sensing the voltage applied to a terminal of an integrated or discrete power device on a semiconductor substrate
A capacitor for sensing a substrate voltage in an integrated circuit power device may be implemented by isolating a portion or segment of the metal layer that normally covers the heavily doped...
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6812487 |
Test key and method for validating the doping concentration of buried layers within a deep trench capacitors
A test key for validating the doping concentration of buried layers within a deep trench capacitor. The test key is deposited in the scribe line region of a wafer. In the test key of the present...
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6812109 |
Integrated decoupling capacitors
A method for fabricating buried decoupling capacitors in an integrated circuit is disclosed. The method forms decoupling capacitors by creating an opening within a substrate which has fin-like...
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6806568 |
Decoupling capacitor for integrated circuit package and electrical components using the decoupling capacitor and associated methods
A capacitive structure is made with thin film capacitor plates substantially surrounding an opening cavity for accommodating a chip. The capacitive structure includes at least one capacitor and is...
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6806542 |
Electronic device having a filled dielectric medium
A solid state electronic device consists of a bottom electrode ( 10 ) and a top electrode ( 20 ) with a dielectric layer ( 30 ) sandwiched in between. In one example, the dielectric layer is...
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6803640 |
Capacitor
The present invention relates to a WACC and a fabricating method thereof to prevent the occurrence of lifting between a polysilicon layer pattern and blocking metal layer of an upper electrode. In...
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6803655 |
Semiconductor integrated circuit device with EMI prevention structure
A power lead and a ground lead are connected to corresponding pads of a die through an intra-package wiring substrate. A ground plane is formed in a mold under the intra-package wiring substrate...
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6800921 |
Method of fabricating a polysilicon capacitor utilizing fet and bipolar base polysilicon layers
A method of forming a poly-poly capacitor, a MOS transistor, and a bipolar transistor simultaneously on a substrate comprising the steps of depositing and patterning a first layer of polysilicon on...
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6800922 |
Semiconductor device with layer peeling resistance
An object of the present invention is to suppress a layer-peeling phenomenon in a semiconductor device comprising at least a ferroelectric layer and an upper electrode formed thereon while...
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6800935 |
Switching circuit with improved signal blocking effect in off mode
A switching circuit includes an insulating substrate including two signal transmission lines; a switching diode mounted, in series between the two signal transmission lines, on the insulating...
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6800923 |
Multilayer analog interconnecting line layout for a mixed-signal integrated circuit
A mixed-signal integrated circuit includes a metal-insulator-metal or polysilicon-insulator-polysilicon capacitor. The electrical path from one electrode of the capacitor passes through a first...
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6798010 |
Ferroelectric memory devices
In the present invention, ferroelectric memory devices using a ferroelectric planarization layer and methods of fabricating the same are disclosed. According to the method of the present invention,...
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6794700 |
Capacitor having a dielectric layer including a group 17 element
The present invention provides a capacitor 300 , a method of manufacture therefor and an integrated circuit including the same. In one embodiment of the invention, the capacitor 300 includes a...
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6794728 |
Capacitive sensors in vehicular environments
Capacitive sensors used to detect force upon a transparency product for detecting and discriminating crash characteristics of a vehicle, as well as capacitive sensors used in conjunction with a...
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6794729 |
Stacked capacitor and method of forming the same as well as semiconductor device using the same and circuit board using the same
A stacked capacitor which comprises: a dielectric layer; a two-dimensional array of terminal electrodes on at least one of first and second surfaces of the dielectric layer; first internal...
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6791163 |
Chip electronic component
A chip electronic component including a ceramic element and terminal electrodes with metal coating thereon formed on the surface of the ceramic element. A glass layer is formed on a part of the...
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6787833 |
Integrated circuit having a barrier structure
This invention relates to contact structures for use in integrated circuits and methods of fabricating contact structures. In one embodiment, a contact structure includes a conductive layer, one or...
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6787795 |
Logic apparatus and logic circuit
A logic apparatus having first and second single-electron devices connected serially or in parallel. Each of the single-electron devices includes a conductive island insulatively disposed between...
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6787438 |
Device having one or more contact structures interposed between a pair of electrodes
A microelectromechanical device is provided which includes a contact structure interposed between a pair of electrodes arranged beneath a beam. In some embodiments, the device may include...
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6781219 |
Semiconductor die assembly having leadframe decoupling characters
A packaged integrated circuit device with a multi-level leadframe has a plurality of integral capacitors formed by placing a thin dielectric layer between a lower leadframe and an upper leadframe,...
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6781185 |
Semiconductor high dielectric constant decoupling capacitor structures and process for fabrication
Apparatus and method for providing high dielectric constant decoupling capacitors for semiconductor structures. The high dielectric constant decoupling capacitor can be fabricated by depositing...
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6777775 |
Semiconductor integrated circuit, D-A converter device, and A-D converter device
A semiconductor integrated circuit has a plurality of capacitor cells, and each capacitor cell has an upper electrode and a lower electrode. These electrodes are respectively connected to an upper...
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6777776 |
Semiconductor device that includes a plurality of capacitors having different capacities
A semiconductor device has a plurality of capacitors. The semiconductor device includes a first capacitor arranged on a substrate and including first upper and lower electrode layers between which...
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6777777 |
High density composite MIM capacitor with flexible routing in semiconductor dies
According to one embodiment, a structure comprises an electrode of a lower MIM capacitor situated in a first interconnect metal layer of a semiconductor die. The structure further comprises a...
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6774459 |
Capacitor layout technique for reduction of fixed pattern noise in a CMOS sensor
A new capacitor architecture includes a front plate of the capacitor formed form a first polysilicon layer. The front plate is surround by first and second dielectric layers. The back plate of the...
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6770907 |
Test structure and methodology for semiconductor stress-induced defects and antifuse based on same test structure
A method for detecting semiconductor process stress-induced defects. The method comprising: providing a polysilicon-bounded test diode, the diode comprising a diffused first region within an upper...
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6768151 |
Semiconductor memory device with memory cells having same characteristics and manufacturing method for the same
In a method of manufacturing a semiconductor memory device, a lower electrode film is formed on a semiconductor substrate via an interlayer insulating film. A ferroelectric film is formed on the...
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6762107 |
Capacitor and manufacturing method thereof
A capacitor ( 1 ) using a flexible substrate ( 2 ) includes a hole portion ( 6 a ) formed in a dielectric ( 6 ) to connect an upper electrode ( 7 ) to an external leader electrode ( 4 ). At least...
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6762109 |
Method of manufacturing semiconductor device with reduced number of process steps for capacitor formation
A method of manufacturing a semiconductor device and a method of forming a capacitor allow the formation of a high-performance capacitor without increasing the number of process steps. A silicide...
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6759728 |
Boost capacitor layout
An H-bridge circuit having a boost capacitor coupled to the gate of the low-side driver. A driver, in the form of a switching transistor is connected between the load and ground, thus providing a...
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