|
Match
|
Document |
Document Title |
|
|
6753567 |
Lanthanum oxide-based dielectrics for integrated circuit capacitors
Lanthanum oxide-based gate dielectrics are provided for integrated circuit field effect transistors. The gate dielectrics may include lanthanum oxide, preferably amorphous lanthanum oxide and/or an...
|
|
|
6750500 |
Capacitor electrode for integrating high K materials
A conductive composition of tantalum nitride is disclosed for use as a conductive element in integrated circuits. The layer is shown employed in a memory cell, and in particular in a cell...
|
|
|
6747334 |
Thin-film capacitor device
A thin-film capacitor device for performing temperature compensation is manufactured by layering a first dielectric thin-film and a second dielectric thin-film, wherein the second dielectric...
|
|
|
6747318 |
Buried channel devices and a process for their fabrication simultaneously with surface channel devices to produce transistors and capacitors with multiple electrical gate oxides
A method for fabricating buried channel NMOS devices and the devices themselves are disclosed. These buried channel NMOS devices are fabricated with a p-type substrate, an n-type implant in the top...
|
|
|
6740901 |
Production of semiconductor integrated circuit
A semiconductor integrated circuit in which the storage capacitor has an increased capacitance and a decreased leakage current. The storage capacitor is formed by the steps of: forming a...
|
|
|
6737728 |
On-chip decoupling capacitor and method of making same
On-chip decoupling capacitor structures, and methods of fabricating such decoupling capacitors are disclosed. In one embodiment of the present invention, a capacitor stack may consist of a bottom...
|
|
|
6734526 |
Oxidation resistant microelectronics capacitor structure with L shaped isolation spacer
A capacitor structure within a microelectronic product employs at least one of: (1) an oxidation barrier layer formed upon a second capacitor plate within the capacitor structure; and (2) a spacer...
|
|
|
6734487 |
Memory integrated circuitry with DRAMs using LOCOS isolations and areas less than 6F2
Memory integrated circuitry includes an array of memory cells formed over a semiconductive substrate and occupying area thereover, at least some memory cells of the array being formed in lines of...
|
|
|
6732335 |
Semiconductor IC with an inside capacitor for a power supply circuit and a method of automatically designing the same
A semiconductor IC (Integrated Circuit) has blocks implemented as a standard cell each. Wirings are arranged in a wiring region for wiring the connections of circuit devices of a standard cell,...
|
|
|
6730950 |
Local interconnect using the electrode of a ferroelectric
Ferroelectric device structures are provided comprising a ferroelectric capacitor, first and second circuit elements, and first and second contacts. The ferroelectric capacitor residing over the...
|
|
|
6720604 |
Capacitor for an integrated circuit
The present invention provides a capacitor comprising a conductive plug comprising a top surface and exposed sidewalls, wherein the sidewalls comprise a layer selected from the group consisting of...
|
|
|
6720603 |
CAPACITOR STRUCTURE AND A SEMICONDUCTOR DEVICE WITH A FIRST METAL LAYER, A SECOND METAL SILICIDE LAYER FORMED OVER THE FIRST METAL LAYER AND A SECOND METAL LAYER FORMED OVER THE SECOND METAL SILICIDE LAYER
A disadvantage upon heat treatment in an oxygen atmosphere of a dielectric film formed on a lower electrode of capacitance device of DRAM that oxygen permeating the lower electrode oxidizes a...
|
|
|
6713836 |
Packaging structure integrating passive devices
In a leadframe packaging structure, a leadframe includes a plurality of first leads, a plurality of second leads, and a die pad. The first leads define a chip-bonding region in which is arranged...
|
|
|
6713840 |
Metal-insulator-metal device structure inserted into a low k material and the method for making same
The present disclosure provides a metal-insulator-metal (MIM) device structure inserted in a low-k material and the method for forming same. The low-k material has a first low-k material layer at...
|
|
|
6713805 |
Semiconductor memory device with increased capacitance
A plurality of capacitors of which the sidewalls, that are storage nodes, extend in the vertical direction are aligned in the horizontal direction. Storage node has a rectangular form made of...
|
|
|
6713846 |
Multilayer high &kgr dielectric films
A new multilayer dielectric film for improving dielectric constant and thermal stability of gate dielectrics is provided. The multilayer dielectric film comprises a first layer formed of a metal...
|
|
|
6710425 |
Structure to increase density of MIM capacitors between adjacent metal layers in an integrated circuit
A high density MIM capacitor structure and method of manufacturing the same is disclosed for integrated circuits having multiple metal layer interconnections. The capacitor structure is formed...
|
|
|
6710426 |
Semiconductor device and transceiver apparatus
A field effect transistor (FET) is formed on a semiconductor substrate. A drain terminal, a source terminal, and a gate terminal connected to the FET are also formed on the semiconductor substrate....
|
|
|
6707091 |
Semiconductor device having capacitor
A semiconductor device having a capacitor according to the present invention has a storage node and a cell plate opposed to each other through a capacitor dielectric layer, and at least either the...
|
|
|
6703681 |
Variable-capacitance capacitor
The invention concerns a variable capacitance capacitor comprising a periodic structure of raised zones ( 5 ) separated by recesses ( 6 ) formed in a type N semiconductor substrate ( 1 ). The walls...
|
|
|
6703705 |
Semiconductor device and method for packaging same
A semiconductor device has an LSI device provided with a plurality of power supply line connection pads and ground line connection pad in a peripheral edge part of a circuit-formation surface,...
|
|
|
6700152 |
Dynamic random access memory including a logic circuit and an improved storage capacitor arrangement
The new structure of a memory cell which enables avoiding the problem of a step without increasing the number of processes, the structure of a semiconductor integrated circuit in which a common...
|
|
|
6700177 |
Compact, surface-mounting-type, electronic-circuit unit
In a surface-mounting-type electronic-circuit unit, circuit elements, including capacitors, resistors, and inductive devices, and electrically conductive patterns connected to the circuit elements...
|
|
|
6696702 |
Silicon carbide semiconductor switching device
An object of the present invention is to improve the relationship between the switching loss and the conduction loss in a semiconductor device comprising a diode and a switching device made of...
|
|
|
6690055 |
Devices containing platinum-rhodium layers and methods
A method of forming a rhodium-containing layer on a substrate, such as a semiconductor wafer, using complexes of the formula L y RhY z is provided. Also provided is a chemical vapor co-deposited...
|
|
|
6691294 |
Method and device for implementing by-pass capacitors
An unused logic portion of a device is identified, where the unused logic portion of the device is part of a metal definable logic portion of the device. The unused logic portion is specified to be...
|
|
|
6680542 |
Damascene structure having a metal-oxide-metal capacitor associated therewith
The present invention provides a semiconductor device, including an interconnect and a capacitor, and a method of fabrication therefor. The method includes forming a damascene interconnect...
|
|
|
6680520 |
Method and structure for forming precision MIM fusible circuit elements using fuses and antifuses
The present invention describes an apparatus and method for fabrication of a precision circuit elements. In particular, the circuit elements are fabricated as part of an integrated circuit...
|
|
|
6677650 |
Silicon plugs and local interconnect for embedded memory and system-on-chip (SOC) applications
A process for fabricating system-on-chip devices which contain embedded DRAM along with other components such as SRAM or logic circuits is disclosed. Local interconnects, via salicides and tungsten...
|
|
|
6674131 |
Semiconductor power device for high-temperature applications
In a SiC substrate ( 10 ), a first active region ( 12 ) composed of n-type heavily doped layers ( 12 a ) and undoped layers ( 12 b ), which are alternately stacked, and a second active region ( 13...
|
|
|
6670692 |
Semiconductor chip with partially embedded decoupling capacitors
A partially embedded decoupling capacitor is provided as an integral part of a semiconductor chip for reducing delta-I noise. The semiconductor chip includes a plurality of embedded metal layers, a...
|
|
|
6670663 |
DRAM cell capacitor and manufacturing method thereof
A method for manufacturing a cell capacitor includes a step of forming an upper electrode and a trench for the lower electrode simultaneously in a single mask step. Further steps for manufacturing...
|
|
|
6664606 |
Multi-layer integrated circuit structure with reduced magnetic coupling
A method of utilizing passive circuit components in an integrated circuit comprising the steps of providing a plurality of integrated capacitive elements and a plurality of integrated inductive...
|
|
|
6661079 |
Semiconductor-based spiral capacitor
Increased capacitance per unit of area with reduced series resistance and inductance is provided by a semiconductor-based capacitor with a spiral shape. The capacitor utilizes a plurality of...
|
|
|
6656826 |
Semiconductor device with fuse to be blown with energy beam and method of manufacturing the semiconductor device
A semiconductor device has a fuse to be blown with an energy beam. The semiconductor device has copper wiring levels formed on a semiconductor substrate on which semiconductor elements are formed,...
|
|
|
6657275 |
Pad and via placement design for land side capacitors
An integrated circuit package and land side capacitor with reduced power delivery loop inductance. The capacitor pads have vias that lie underneath the land side capacitor, and have interposed digits.
|
|
|
6656766 |
Semiconductor device having chip scale package
A first surface of a semiconductor chip and an upper surface of a circuit board are bonded with a pad of the semiconductor chip fitted to a first opening of the circuit board. The pad is...
|
|
|
6653230 |
Semiconductor device having concave electrode and convex electrode and method of manufacturing thereof
It is intended to enable simultaneous formation of concave capacitor storage electrodes and a convex bit contact plug electrode and thereby makes it possible to reduce spaces of margins for...
|
|
|
6653858 |
Bypass capacitance localization
Localizing bypass capacitance for the purpose of reducing or eliminating noise in power supplies in an integrated circuit (IC). After a data path block of macro cells has been constructed by the IC...
|
|
|
6649998 |
Passive devices and modules for transceiver
A passive device and module for a transceiver, and a manufacturing method thereof are provided. The passive device includes a semiconductor or a dielectric substrate, at least one capacitor, at...
|
|
|
6649999 |
Semiconductor chip configuration with a layer sequence with functional elements contacted by contact pads
In a semiconductor chip, conductive tracks run in a rewiring layer from contact pads to contact elevations. The contact pads are formed as vias. The conductive tracks are constructed in sections as...
|
|
|
6649958 |
Semiconductor device with MIS capacitors sharing dielectric film
A semiconductor device having an MIS capacitor having a low capacitance value and an MIS capacitor having a high capacitance value, and to a manufacturing method thereof. One MIS capacitor consists...
|
|
|
6646298 |
Capacitor with oxygenated metal electrodes and high dielectric constant materials
A stabilized capacitor using high dielectric constant dielectric materials, such as Ta 2 O 5 and Ba x Sr (1-x) TiO 3 , and methods of making such capacitors are provided. A preferred method...
|
|
|
6646321 |
Power transistor with internally combined low-pass and band-pass matching stages
RF power transistor provided with an internal shunt inductor, characterized in that the shunt is produced in two separated, capacitors (Cb, Cp), each internally bonded to the transistor internal...
|
|
|
6645779 |
FeRAM (ferroelectric random access memory) and method for forming the same
A ferroelectric random access memory (FeRAM) device including a semiconductor substrate, a transistor, a first interlayer insulating film formed on the transistor, a plug buried in a contact hole...
|
|
|
6646323 |
Zero mask high density metal/insulator/metal capacitor
The present invention is directed to a structure and method of forming an integrated circuit MIM capacitor having a relatively capacitance without the need for an additional mask step. Methods of...
|
|
|
6639299 |
Semiconductor device having a chip size package including a passive element
A semiconductor device includes a semiconductor substrate on which a circuit element forming region and a plurality of connection pads are formed, a first columnar electrode which is formed on a...
|
|
|
6633197 |
Gate capacitor stress reduction in CMOS/BICMOS circuit
Method and apparatus for using a MOSFET having a thin gate oxide layer as a gate capacitor is provided. The method includes the steps of biasing at least one of a source and a drain of the MOSFET...
|
|
|
6630707 |
Semiconductor device including logic circuit and memory circuit
The semiconductor device with its primary bit line and secondary bit lines, according to the present invention, is capable of being accessed at a high speed. In this semiconductor device, any one...
|
|
|
6627971 |
Polysilicon structures with different resistance values for gate electrodes, resistors, and capacitor plates
A device with a plurality of structures with different resistance values is formed on a substrate. A polysilicon layer is formed upon the substrate. A silicon oxide layer is formed over the...
|