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6856002 |
Graded GexSe100-x concentration in PCRAM
The present invention provides a design for a PCRAM element which incorporates multiple metal-containing germanium-selenide glass layers of diverse stoichiometries. The present invention also...
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6849929 |
IC chip and semiconductor device
An IC chip has externally and selectively cuttable members F 1 -F 3 , which can be cut, or cut open, at more than one cuttable points C 1 and C 2 . So long as at least one of the multiple cuttable...
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6844609 |
Antifuse with electrostatic assist
A structure and method for providing an antifuse which is closed by laser energy with an electrostatic assist. Two or more metal segments are formed over a semiconductor structure with an air gap...
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6841846 |
Antifuse structure and a method of forming an antifuse structure
The present invention comprises an antifuse having a hemispherical grained (HSG) layer and a method of forming antifuse having a hemispherical grained (HSG) layer. The antifuse of the present...
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6841425 |
Wafer treatment method for protecting fuse box of semiconductor chip
Methods for treating a wafer to protect a fuse box of a semiconductor chip are provided. These methods include applying an insulating coating solution onto the surface of at least one of a...
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6838367 |
Method for simultaneous formation of fuse and capacitor plate and resulting structure
An improved method for forming a fuse element is disclosed. During the formation of the upper capacitor plate in a capacitor structure, metals or their alloys are simultaneously patterned as an...
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6835998 |
Fuse area structure including protection film on sidewall of fuse opening in semiconductor device and method of forming the same
A fuse area structure in a semiconductor device and a method of forming the same are provided. The fuse area structure includes a protection film formed of a passivation film for preventing...
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6836398 |
System and method of forming a passive layer by a CMP process
The present invention provides systems and methods that facilitate formation of semiconductor devices via planarization processes. The present invention utilizes dishing effects that typically...
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6831349 |
Method of forming a novel top-metal fuse structure
A method of forming a top-metal fuse structure comprising the following steps. A structure having an intermetal dielectric layer is formed thereover the structure including a fuse region and an...
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6828653 |
Method of forming metal fuses in CMOS processes with copper interconnect
The present invention provides a method of forming a semiconductor device fuse and a semiconductor device fuse structure. A first dielectric layer is formed on top of a metal layer in a...
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6828652 |
Fuse structure for semiconductor device
A fuse structure ( 30 ) formed in a semiconductor device is provided. The fuse structure ( 30 ) includes a layer of fuse material ( 32 ), a first contact ( 40 ), and a second contact ( 42 ). The...
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6825107 |
Method for fabricating a memory chip
An ovonic phase-change semiconductor memory device having a reduced area of contact between electrodes of chalcogenide memories, and methods of forming the same. Such memory devices are formed by...
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6822311 |
DC or AC electric field assisted anneal
A method for forming a desired junction profile in a semiconductor device. At least one dopant is introduced into a semiconductor substrate. The at least one dopant is diffused in the semiconductor...
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6822310 |
Semiconductor integrated circuit
A semiconductor integrated circuit according to the invention includes a wiring member formed on a main face of a semiconductor substrate, a fusing member connected to the wiring member and having...
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6822309 |
Apparatus for selectively cutting fuse electrodes
Adjacent ones of a plurality of fuse electrodes extending parallel to each other are cut off by a laser beam. Cutting positions on the adjacent fuse electrodes are set to positions which are...
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6818997 |
Semiconductor constructions
The invention includes a dual-damascene semiconductor processing method. A semiconductor substrate is provided, and the substrate includes a conductive structure and an insulative layer over the...
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6818957 |
Semiconductor chip with fuse unit
A semiconductor chip includes a logic circuit unit, at least one memory macro unit having a redundant memory cell which recovers a defect cell, electrode pad rows being arranged around the outside...
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6815265 |
Method of fabricating a semiconductor device with a passivation film
An uppermost interlayer isolation film is provided on a semiconductor substrate. An uppermost wire is provided on the uppermost interlayer isolation film. A silicon oxide film is provided to cover...
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6809398 |
Metal-to-metal antifuse structure and fabrication method
A metal-to-metal antifuse according to the present invention is compatible with a Cu dual damascene process and is formed over a lower Cu metal layer planarized with the top surface of a lower...
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6809397 |
Fuse boxes with guard rings for integrated circuits and integrated circuits including the same
Integrated circuit devices and fuse boxes have a fuse line at a fuse portion of the integrated circuit device and a first insulating layer on the fuse line. A first guard ring pattern is provided...
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6806528 |
Phase-changeable memory devices having phase-changeable material regions with lateral contacts and methods of fabrication therefor
A phase-changeable memory device comprises a substrate and an access transistor formed in and/or on the substrate. Laterally spaced apart first and second conductive patterns are disposed on the...
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6806107 |
Electrical fuse element test structure and method
A method of monitoring heat dissipation behavior of a fuse element formed in an integrated circuit structure is provided. A fuse element is fabricated in an integrated circuit structure. A...
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6806551 |
Fuse construction for integrated circuit structure having low dielectric constant dielectric material
Fuses, and optionally metal pads, are formed over a layer of low k dielectric material structure having first openings lined with conductive barrier material and filled to form metal interconnects...
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6800919 |
Semiconductor device having a redundancy function
A semiconductor device includes first to third functional areas parted each other by a boundary region on a semiconductor substrate. A memory block is formed in the first functional area and...
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6797979 |
Metal structure for a phase-change memory device
The invention relate to a damascene chalcogenide memory cell structure. The damascene chalcogenide memory cell structure is fabricated under conditions that simplify previous process flows. The...
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6791157 |
Integrated circuit package incorporating programmable elements
An integrated circuit package includes at least one one-time programmable element, such as a fuse, having a first and a second end separated by a programmable link. The first end of the one-time...
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6791102 |
Phase change memory
Briefly, in accordance with an embodiment of the invention, a phase change memory and a method to manufacture a phase change memory is provided. The phase change memory may include a phase change...
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6787878 |
Semiconductor device having a potential fuse, and method of manufacturing the same
In a semiconductor device, an active region is formed in a semiconductor substrate separated by a plurality of isolation regions. A plurality of surface insulating films of different thickness are...
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6787886 |
Semiconductor device and methods of fabricating the same
A semiconductor device includes a semiconductor substrate which has a major surface and a MOS transistor which has a gate and first and second diffusion regions and which is formed on the major...
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6784044 |
High dopant concentration diffused resistor and method of manufacture therefor
The present invention provides a high dopant concentration diffused resistor, a method of manufacture therefor, and an integrated circuit including the same. In one embodiment of the invention, the...
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6781145 |
Controlable ovonic phase-change semiconductor memory device
An ovonic phase-change semiconductor memory device having a reduced area of contact between electrodes of chalcogenide memories, and methods of forming the same are disclosed. Such memory devices...
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6774456 |
Configuration of fuses in semiconductor structures with Cu metallization
A configuration of fuses in a semiconductor structure having Cu metallization planes is provided. The semiconductor structure has an Al metal layer on the topmost interconnect plane for providing...
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6770947 |
Laser-breakable fuse link with alignment and break point promotion structures
A severable horizontal portion of a fuse link is formed relative to a vertically configured structure in an IC to promote separation of the severable portion upon applying energy from a laser beam....
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6770949 |
One-mask customizable phase-locked loop
A system and method in accordance with the invention minimizes the redesign burden in tuning and/or customizing PLLs on ICs. Variable resistors are placed in the PLL in places that facilitate...
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6768150 |
Magnetic memory
A magnetic memory cell is disclosed. The memory cell includes first conductor and second conductors coupled to first and second electrodes of a magnetic element. A plurality of memory cells is...
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6768185 |
Formation of antifuse structure in a three dimensional memory
The present invention is directed to novel antifuse arrays and their methods of fabrication. According to an embodiment of the present invention an array comprises a plurality of first spaced apart...
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6768199 |
Flip chip type semiconductor device and method of fabricating the same
A flip chip type semiconductor device comprises at least one first metal line and at least a pair of second metal lines formed in the passivation layer, an aluminum pad covering the first metal...
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6762501 |
Low stress integrated circuit copper interconnect structures
Isolated metal structures ( 110 ), ( 140 ) are formed adjacent to terminated metal lines ( 100 ), ( 130 ) that are connect by a via ( 120 ). The isolated structures ( 110 ), ( 140 ) act to suppress...
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6762442 |
Semiconductor device carrying a plurality of circuits
A semiconductor device includes on the same chip at least an I/O region where an input/output pad is formed and active regions where a circuit can be mounted, where a plurality of logic circuits...
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6756256 |
Method for preventing burnt fuse pad from further electrical connection
A method for preventing burnt fuse pads from further electrical connection suitable before the formation of bumps on the wafer. A dielectric layer is formed over the active surface of the wafer...
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6756655 |
Fuse for a semiconductor configuration and method for its production
A semiconductor configuration is described which includes a semiconductor body having a main surface and an insulator layer disposed on the main surface of the semiconductor body. The insulator...
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6753590 |
High impedance antifuse
A programmable element that has a first diode having an electrode and a first insulator disposed between the substrate and said electrode of said first device, said first insulator having a first...
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6750470 |
Robust field emitter array design
There is provided a field emitter device formed over a semiconductor substrate. The field emitter device includes at least one field emitter tip disposed over the substrate, and a conducting gate...
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6750529 |
Semiconductor devices including fuses and multiple insulation layers
A semiconductor device may include a fuse section 110 in which a plurality of fuses 20 to be fused by irradiation of a laser beam are formed. The fuses 20 are arranged at a specified pitch. A...
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6750129 |
Process for forming fusible links
A process for forming fusible links in an integrated circuit in which the fusible links are formed in the final metallization layer simultaneously with bonding pads. The process can be applied in...
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6737726 |
Resistance variable device, analog memory device, and programmable memory cell
In one implementation, a non-volatile resistance variable device includes a body formed of a voltage or current controlled resistance setable material, and at least two spaced electrodes on the...
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6737345 |
Scheme to define laser fuse in dual damascene CU process
A method of fabrication used for semiconductor integrated circuit devices to define a thin copper fuse at a top via opening, in a partial etch, dual damascene integration scheme, efficiently...
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6737686 |
Non-volatile programmable memory device
A memory cell includes a heating component that is connected to a voltage-breakdown component. The heating component is configured to accelerate the break-down of a voltage-breakdown component....
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6734525 |
Low stress integrated circuit fusible link
A fuse structure and method for fabricating same are disclosed. The fuse structure is designed for opening by conventional laser energy application. The fuse structure is characterized by an...
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6730982 |
FBEOL process for Cu metallizations free from Al-wirebond pads
A process of making an interconnection structure of Cu FBEOL semiconductor devices that does not rely upon Al-wirebond pads which require additional patterning steps (for Al-via to Cu, Al-pad),...
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