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7622778 |
Semiconductor device having shallow trench isolation structure comprising an upper trench and a lower trench including a void
In one embodiment, a semiconductor device has an active region defined by an isolation layer formed inside an STI trench that includes an upper trench and a lower trench having a substantially...
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7619294 |
Shallow trench isolation structure with low trench parasitic capacitance
Provided are methods and composition for forming an isolation structure on an integrated circuit substrate. First, a trench is etched in the integrated circuit substrate. A lower dielectric layer...
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7612427 |
Apparatus for confining inductively coupled surface currents
A deep n-well is formed beneath the area of an inductor coil. The use of a deep n-well lessens the parasitic capacitance by placing a diode in series with the interlayer dielectric cap. The deep...
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7608908 |
Robust deep trench isolation
Higher voltage device isolation structures ( 40, 60, 70, 80, 90, 90 ′) are provided for semiconductor integrated circuits having strongly doped buried layers ( 24, 24 ″). One or more dielectric...
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7608870 |
Isolation trench geometry for image sensors
A pixel cell including a substrate having a top surface. A photo-conversion device is at a surface of the substrate and a trench is in the substrate adjacent the photo-conversion device. The trench...
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7605442 |
Semiconductor device
A semiconductor device comprises a semiconductor substrate, a plurality of transistors provided in the semiconductor substrate, and an isolation region for isolating the plurality of transistors to...
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7605429 |
Hybrid crystal orientation CMOS structure for adaptive well biasing and for power and performance enhancement
The present invention provides a semiconducting structure including a substrate having an SOI region and a bulk-Si region, wherein the SOI region and the bulk-Si region have a same or differing...
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7598590 |
Semiconductor chip and method for manufacturing the same and semiconductor device
The semiconductor chip 1 has a semiconductor substrate 10 . In the present embodiment, the semiconductor substrate 10 , which is an SOI substrate, is constituted by comprising a support...
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7592684 |
Semiconductor device and method for manufacturing the same
A semiconductor device is provided in which high breakdown voltage transistors and low voltage driving transistors are formed on the same substrate. The device includes a semiconductor layer, first...
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7592676 |
Semiconductor device with a transistor having different source and drain lengths
A cell includes a plurality of diffusion region pairs, each of the diffusion region pairs being formed by a first impurity diffusion region which is a constituent of a transistor and a second...
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7589391 |
Semiconductor device with STI and its manufacture
A semiconductor device includes: a silicon substrate with semiconductor elements; an isolation trench formed in the silicon substrate for isolating active regions in the silicon substrate, the...
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7586158 |
Piezoelectric stress liner for bulk and SOI
A preferred embodiment of the invention provides a semiconductor device. A preferred device comprises an n-channel transistor and a p-channel transistor disposed in a semiconductor body and a...
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7586150 |
Semiconductor devices with local recess channel transistors and methods of manufacturing the same
A method of manufacturing a local recess channel transistor in a semiconductor device. A hard mask layer is formed on a semiconductor substrate that exposes a portion of the substrate. The exposed...
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7582949 |
Semiconductor devices
A design structure embodied in a machine readable medium used in a design process. The design structure includes a first sub-collector formed in an upper portion of a substrate and a lower portion...
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7582947 |
High performance device design
A semiconductor structure having a recessed active region and a method for forming the same are provided. The semiconductor structure comprises a first and a second isolation structure having an...
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7582935 |
Methods for manufacturing SOI substrate using wafer bonding and complementary high voltage bipolar transistor using the SOI substrate
A method of manufacturing an SOI substrate for semiconductor devices is described. The method includes forming a low density impurity region in a first semiconductor substrate and a high density...
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7572713 |
Method of fabricating semiconductor device with STI structure
A semiconductor device such as a flash memory includes a semiconductor substrate having a surface, and a plurality of trenches formed in the substrate so as to be open at the surface of the...
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7560357 |
Method for creating narrow trenches in dielectric materials
A method for producing narrow trenches in semiconductor devices. The narrow trenches are formed by chemically changing the properties of a first dielectric layer locally, such that the side walls...
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7557422 |
Semiconductor device with STI structure
A semiconductor device includes a semiconductor substrate including a memory cell region and a peripheral circuit region, a first trench formed in the memory cell region and having a first depth...
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7557415 |
Trench isolation type semiconductor device and related method of manufacture
A semiconductor device and related method of manufacture are disclosed. The device comprises; a trench having a corner portion formed in the semiconductor substrate, a first oxide film formed on an...
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7556990 |
CMOS image sensor having improved signal efficiency and method for manufacturing the same
A CMOS image sensor and a method for manufacturing the same improves signal efficiency by reducing a dark signal, and includes a substrate having a first conductive type comprising an image area...
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7550816 |
Filled trench isolation structure
A method for depositing a dielectric in a trench on a semiconductor substrate is provided. The dielectric is deposited by using an HDP-CVD system and performing a deposition of first and second...
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7550815 |
Semiconductor device and method of producing the same
In a semiconductor device having element isolation made of a trench-type isolating oxide film 13 , large and small dummy patterns 11 of two types, being an active region of a dummy, are located...
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7550343 |
Forming a semiconductor structure in manufacturing a semiconductor device using one or more epitaxial growth processes
In one embodiment, a semiconductor structure used in manufacturing a semiconductor device includes a substrate layer. The structure also includes first and second isolation regions formed by...
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7544607 |
Semiconductor device having thin film formed by atomic layer deposition and method for fabricating the same
A semiconductor device having a thin film formed by atomic layer deposition and a method for fabricating the same, wherein the semiconductor device includes a liner layer formed on an internal wall...
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7541629 |
Embedded insulating band for controlling short-channel effect and leakage reduction for DSB process
A method and structure for reducing leakage currents in integrated circuits based on a direct silicon bonding (DSB) fabrication process. After recessing a top semiconductor layer and an underlying...
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7541298 |
STI of a semiconductor device and fabrication method thereof
A method for filling silicon oxide materials into a trench includes providing a substrate having a plurality of trenches, performing a first deposition process to form a first silicon oxide layer...
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7538409 |
Semiconductor devices
A device comprises a first sub-collector formed in an upper portion of a substrate and a lower portion of a first epitaxial layer and a second sub-collector formed in an upper portion of the first...
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7535077 |
Method for manufacturing a semiconductor device including a shallow trench isolation structure
A semiconductor device having a semiconductor substrate includes an active region for forming transistors in which a gate is installed. An element isolation region for isolating each of transistors...
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7525186 |
Stack package having guard ring which insulates through-via interconnection plug and method for manufacturing the same
A stack package comprises a substrate having a circuit pattern; at least two semiconductor chips stacked on the substrate, having a plurality of through-via interconnection plugs and a plurality of...
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7521763 |
Dual stress STI
The embodiments of the invention provide a device, method, etc. for a dual stress STI. A semiconductor device is provided having a substrate with a first transistor region and a second transistor...
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7518210 |
Trench isolated integrated circuit devices including grooves
Trench isolated integrated circuit devices are fabricated by forming a trench including sidewalls in an integrated circuit substrate, and forming a lower device isolation layer in the trench and...
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7504704 |
Shallow trench isolation process
A structure including a transistor and a trench structure, with the trench structure inducing only a portion of the strain in a channel region of the transistor.
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7501691 |
Trench insulation structures including an oxide liner and oxidation barrier
A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a liner layer preferably is deposited...
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7501686 |
Semiconductor device and method for manufacturing the same
A semiconductor device is disclosed that includes a semiconductor substrate, a device region disposed at a predetermined location of the semiconductor substrate, and a shallow trench isolation...
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7495308 |
Semiconductor device with trench isolation
A semiconductor device includes a semiconductor substrate including a plurality of trenches formed along a first direction and a plurality of first upper surfaces divided by the trenches, a...
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7485943 |
Dielectric isolation type semiconductor device and manufacturing method therefor
A dielectric isolation type semiconductor device includes a dielectric isolation type substrate in which a support substrate, an embedded dielectric layer, and a first conductive type semiconductor...
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7482671 |
MOS semiconductor device isolated by a device isolation film
A MOS semiconductor device isolated by a trench device isolation region includes a p-channel MOS field effect transistor having a source/drain region with a length in the channel direction that is...
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7482662 |
High voltage semiconductor device utilizing a deep trench structure
A semiconductor device includes a substrate having a source, a drain, and a gate between the source and the drain. Both the source and the drain include a first edge, and the gate includes a first...
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7482656 |
Method and structure to form self-aligned selective-SOI
Methods of forming a self-aligned, selective semiconductor on insulator (SOI) structure and a related structure are disclosed. In one embodiment, a method includes providing a substrate; forming a...
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7479688 |
STI stress modification by nitrogen plasma treatment for improving performance in small width devices
A method for modulating the stress caused by bird beak formation of small width devices by a nitrogen plasma treatment. The nitrogen plasma process forms a nitride liner about the trench walls that...
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7476938 |
Transistor having dielectric stressor elements at different depths from a semiconductor surface for applying shear stress
A chip is provided which includes an active semiconductor region and a field effect transistor (“FET”) having a channel region, a source region and a drain region all disposed within the active...
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7466005 |
Recessed termination for trench schottky device without junction curvature
A trench type Schottky device has a guard ring diffusion of constant depth between the outermost of an active trench and an outer surrounding termination trench. The junction curvature of the guard...
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7462907 |
Method of increasing erase speed in memory arrays
A memory array and a method of increasing erase speed therein are provided. The memory array includes a plurality of memory devices organized in rows and columns, where a plurality of bitlines are...
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7453135 |
Semiconductor device and method of manufacturing the same
Plural trench isolation films are provided with portions of an SOI layer interposed therebetween in a surface of the SOI layer in a resistor region (RR) where a spiral inductor (SI) is to be...
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7449763 |
Method of fabricating cell of nonvolatile memory device with floating gate
This disclosure provides cells of nonvolatile memory devices with floating gates and methods for fabricating the same. The cell of the nonvolatile memory device includes device isolation layers in...
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7439605 |
Semiconductor device and method for manufacturing the same
A semiconductor device include a plurality of active element cells including first element regions of a first conductivity type and second element regions of a second conductivity type, the second...
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7439604 |
Method of forming dual gate dielectric layer
A semiconductor device includes a dual gate dielectric layer that increases a performance of a semiconductor device. The semiconductor device includes a first dielectric layer having a...
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7439602 |
Semiconductor device and its manufacturing method
A semiconductor device including memory cells isolated by a trench that may be self aligned with a stacked film pattern ( 7 ) has been disclosed. The memory cells may be flash memory cells having...
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7420259 |
Semiconductor device having two-layered charge storage electrode
A first insulation film, a first conductor film, and a cap are sequentially formed on a semiconductor substrate. The first insulation film, the first conductor film, and the cap, and the substrate...
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