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7420259 Semiconductor device having two-layered charge storage electrode  
A first insulation film, a first conductor film, and a cap are sequentially formed on a semiconductor substrate. The first insulation film, the first conductor film, and the cap, and the substrate...
7417298 High voltage insulated-gate transistor  
An insulated-gate transistor, includes a semiconductor material layer having a front surface, a body region, an insulated gate disposed over the body region with interposition of a gate dielectric,...
7414298 Super self-aligned collector device for mono-and hetero bipolar junction transistors, and method of making same  
The invention relates to a process of forming a compact bipolar junction transistor (BJT) that includes forming a self-aligned collector tap adjacent the emitter stack and an isolation structure. A...
7411269 Isolation structure configurations for modifying stresses in semiconductor devices  
An apparatus and methods for modifying isolation structure configurations for MOS devices to either induce or reduce tensile and/or compressive stresses on an active area of the MOS devices. The...
7411268 Fabricating deeper and shallower trenches in semiconductor structures  
Crossing trenches of different depths may be formed in the same semiconductor structure by etching the deeper trench first. The deeper trench and the substrate may then be covered with a material...
7405461 Semiconductor device and method for manufacturing semiconductor device  
A highly reliable semiconductor device that controls both defects and impurity diffusion and a method for manufacturing such a semiconductor device. An N + embedment layer and an N-type epitaxial...
7402886 Memory with self-aligned trenches for narrow gap isolation regions  
Self-aligned trench filling is used to isolate devices in high-density integrated circuits. A deep, narrow trench isolation region is formed in a substrate between devices. The trench region...
7402885 LOCOS on SOI and HOT semiconductor device and method for manufacturing  
One or more local oxidation of silicon (LOCOS) regions may be formed that apply compressive strain to a channel of a field-effect transistor such as a P-type field-effect transistor (PFET) or other...
7397128 Semiconductor device and method of manufacturing the same  
Disclosed is a semiconductor device in which emitter pad electrodes connected to an active region, collector and base pad electrodes are formed on a surface of a semiconductor substrate....
7397105 Apparatus to passivate inductively or capacitively coupled surface currents under capacitor structures  
A deep n-well is formed beneath the area of a capacitor structure. The use of a deep n-well lessens the parasitic capacitance by placing a diode in series with the interlayer dielectric cap. The...
7397104 Semiconductor integrated circuit device and a method of manufacturing the same  
A semiconductor integrated circuit device is provided which includes an active region, a shallow groove isolation adjacent to the active region, and a semiconductor element formed in the active...
7391096 STI structure  
An STI structure and fabricating method thereof are disclosed. The STI fabricating method comprises forming a pad oxide layer and a first nitride layer on a substrate. A trench is formed by etching...
7391077 Vertical type semiconductor device  
Provided is a semiconductor device including a semiconductor substrate which includes a first semiconductor layer of a first conductivity and a pair of second semiconductor layers disposed on the...
7388263 Shallow trench isolation dummy pattern and layout method using the same  
A dummy cell pattern for shallow trench isolation (STI). Active and shallow trench isolation areas are bounded by a circumference. An active area pattern completely overlaps the active area and a...
7385256 Transistor arrangement in monocrystalline substrate having stress exerting insulators  
In order to insulate active areas of n-type FETs and p-type FETs, insulator structures which due to production exert a tensile stress or a compressive stress on the respectively neighboring active...
7384854 Method of forming low capacitance ESD robust diodes  
A method of forming a diode having a capacitance below 0.1 pF and a breakdown voltage of at least 500V. The method including forming an anode of a first conductivity type and a cathode of a second...
7382016 Semiconductor device and method of manufacturing the same  
A semiconductor device is disclosed, which comprises trench type device isolation regions formed in a semiconductor substrate, semiconductor active regions electrically isolated by the isolation...
7382015 Semiconductor device including an element isolation portion having a recess  
A non-volatile semiconductor memory device, which is intended to prevent data destruction by movements of electric charges between floating gates and thereby improve the reliability, includes...
7368800 Methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating memory circuitry, integrated circuitry and memory integrated circuitry  
The invention includes methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating integrated circuitry including memory circuitry, and integrated...
7358588 Trench isolation type semiconductor device which prevents a recess from being formed in a field region  
A trench isolation type semiconductor device in which a recess is prevented from being formed in a field region and a method of fabricating the same are provided. The trench isolation type...
7358587 Semiconductor structures  
In one aspect, the invention includes a method of forming a material within an opening, comprising: a) forming an etch-stop layer over a substrate, the etch-stop layer having an opening extending...
7358586 Silicon-on-insulator wafer having reentrant shape dielectric trenches  
A bonded SOI wafer and a method for forming a bonded SOI wafer are provided. According to the disclosed method, a first semiconductor wafer is provided, having a first dielectric layer disposed at...
7358558 Flash memory device  
A floating gate of a flash memory device is formed in a moat formed in an isolation film. Therefore, an electric field applied between a control gate and a channel region upon cycling can be...
7358551 Structure and method for improved stress and yield in pFETs with embedded SiGe source/drain regions  
The present invention provides a technique for forming a CMOS structure including at least one pFET that has a stressed channel which avoids the problems mentioned in the prior art. Specifically,...
7355262 Diffusion topography engineering for high performance CMOS fabrication  
Semiconductor structures are formed using diffusion topography engineering (DTE). A preferred method includes providing a semiconductor substrate, forming trench isolation regions that define a...
7355242 Semiconductor device  
A semiconductor device includes: a silicon substrate, having a main surface, in which trenches are formed; element isolation oxide films filling in trenches; a tunnel oxide film, formed on main...
7354834 Semiconductor devices and methods to form trenches in semiconductor devices  
Semiconductor devices and methods of fabricating the same are disclosed. One example method may include forming sequentially a pad oxide film and a silicon nitride film on an entire surface of a...
7354786 Sensor element with trenched cavity  
A micromechanical sensor element and a method for the production of a micromechanical sensor element that is suitable, for example in a micromechanical component, for detecting a physical quantity....
7351661 Semiconductor device having trench isolation layer and a method of forming the same  
A semiconductor device having a trench isolation layer in a semiconductor substrate is provided, wherein the trench isolation layer includes a silicon nitride liner, a silicon oxide liner; and a...
7348639 Method for providing a deep connection to substrate or buried layer in a semiconductor device  
A system and method is disclosed for providing a deep connection to a substrate or buried layer of a semiconductor device. Three shallow trenches are etched halfway through a layer of epitaxial...
7348638 Rotational shear stress for charge carrier mobility modification  
A semiconductor structure and its method of fabrication utilize a semiconductor substrate having an active region mesa surrounded by an isolation trench. A first isolation region having a first...
7339253 Retrograde trench isolation structures  
Methods are provided for making retrograde trench isolation structures with improved electrical insulation properties. One method comprises the steps of: forming a retrograde trench in a silicon...
7339252 Semiconductor having thick dielectric regions  
A method of manufacturing a semiconductor device includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The method also includes providing in the...
7339251 Shallow trench isolation structure and formation method thereof  
A method for fabricating an STI structure in a semiconductor device is disclosed. A disclosed method comprises: forming a pad oxide layer and a pad nitride layer on a substrate in sequence;...
7332789 Isolation trenches for memory devices  
Methods and apparatus are provided. A first dielectric plug is formed in a portion of a trench that extends into a substrate of a memory device so that an upper surface of the first dielectric plug...
7332407 Method and apparatus for a semiconductor device with a high-k gate dielectric  
A process and apparatus for a high-k gate dielectric MOS transistor is described. A substrate is provided, a high-k gate dielectric material is deposited over the substrate, a gate electrode layer...
7327009 Selective nitride liner formation for shallow trench isolation  
A method for forming a divot free nitride lined shallow trench isolation (STI) feature including providing a substrate including an STI trench extending through an uppermost hardmask layer into a...
7326983 Selective silicon-on-insulator isolation structure and method  
A first aspect of the present invention is a method of forming an isolation structure including: (a) providing a semiconductor substrate; (b) forming a buried N-doped region in the substrate; (c)...
7323745 Top drain MOSFET  
A power MOSFET is disclosed in which the source and drain regions are reversed from their usual positions and the drain is on the top of the chip (the surface containing the junction pattern...
7315073 Semiconductor device having an oxide film formed on a semiconductor substrate sidewall of an element region and on a sidewall of a gate electrode  
A first isolation is formed on a semiconductor substrate, and a first element region is isolated via the first isolation. A first gate insulating film is formed on the first element region, and a...
7304365 Semiconductor device and method of producing the same  
In a semiconductor device having element isolation made of a trench-type isolating oxide film 13 , large and small dummy patterns 11 of two types, being an active region of a dummy, are located...
7297995 Transparent metal shielded isolation for image sensors  
An isolation region formed in a substrate and lined with a transparent metal layer. The isolation region provides isolation between adjacent active areas of an integrated circuit structure, for...
7294903 Transistor assemblies  
Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry are described. In one...
7291894 Vertical charge control semiconductor device with low output capacitance  
In accordance with an embodiment of the present invention, a MOSFET includes at least two insulation-filled trench regions laterally spaced in a first semiconductor region to form a drift region...
7285433 Integrated devices with optical and electrical isolation and method for making  
The invention is directed to a method for optical and electrical isolation between adjacent integrated devices. The method comprises the steps of forming at least one trench through an exposed...
7279770 Isolation techniques for reducing dark current in CMOS image sensors  
A structure for isolating areas in a semiconductor device is provided. The structure includes a trench having first and second portions formed in a substrate. The first portion has a first width,...
7279769 Semiconductor device and manufacturing method thereof  
To suppress occurrence of dislocation in a substrate of a semiconductor device at an end portion of a gate electrode. Provided is a semiconductor device having a plurality of element formation...
7276774 Trench isolation structures for integrated circuits  
A dielectric film is formed by atomic layer deposition to conformally fill a narrow, deep trench for device isolation. The method of the illustrated embodiments includes alternately pulsing...
7276769 Semiconductor integrated circuit device  
In a semiconductor integrated circuit device, semiconductor elements formed in active regions included in a first element formation portion (stress transition region) in a peripheral circuit...
7274084 Enhanced PFET using shear stress  
A semiconductor device structure includes a gate structure disposed on a portion of substrate, source and drain regions disposed adjacent to the portion so as to form a channel region in the...
Matches 1 - 50 out of 654 1 2 3 4 5 6 7 8 9 10 11 12 13 14 >