Matches 401 - 450 out of 574 < 1 2 3 4 5 6 7 8 9 10 11 12 >
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6140691 Trench isolation structure having a low K dielectric material isolated from a silicon-based substrate  
A trench isolation structure is provided which includes a dielectric material having a relatively low dielectric constant, K, that is approximately less than 3.8. The capacitance between active...
6137152 Planarized deep-shallow trench isolation for CMOS/bipolar devices  
The trench isolation structure in the present invention is as follows. A lower-half trench is in the substrate. An upper-half trench in the substrate is located above the lower-half trench and the...
6133611 MOS semiconductor device  
In a CMOS circuit including a source diffusion layer and a well region which are at the same potential, a P + -type source diffusion layer and an N + -type substrate diffusion layer are formed in...
6127719 Subfield conductive layer and method of manufacture  
A subfield conductive layer is provided, wherein a conductive layer is implanted beneath and laterally adjacent a field dielectric. The subfield conductive layer is placed within the silicon...
6124623 Semiconductor device having channel stop regions  
An object of the present invention is to manufacture a semiconductor device excellent in withstand-voltage property of each element formed in a peripheral element region portion, without incurring...
6121668 Semiconductor device provided with conductor electrically connected to conducting region  
A conductor crossing a trench around an electrical component is electrically connected to an isolated intermediate conducting region in order to move the field strength concentrations out of the...
6118167 Polysilicon coated nitride-lined shallow trench  
A polycrystalline silicon coated nitride-lined shallow trench technique for isolating active regions on an integrated circuit involves reducing the oxide encroachment and the "bird's beak"...
6107670 Contact structure of semiconductor device  
Disclosed is a contact structure between the bit line and the source/drain region in an EEPROM. An element region is isolated by a trench type element isolation region in a silicon substrate. The...
6103020 Dual-masked field isolation  
A field isolation process utilizes two or more isolation formation steps to form active areas on a semiconductor substrate. Each field isolation step forms a portion of the field isolation in a...
6097076 Self-aligned isolation trench  
The present invention relates to a method for forming an isolation trench structure in a semiconductor substrate without causing deleterious topographical depressions in the upper surface thereof...
6097072 Trench isolation with suppressed parasitic edge transistors  
An integrated circuit device includes a substrate having a planar surface and isolating trenches etched from the substrate. The isolating trenches form edges and corners with the surface of the...
6097069 Method and structure for increasing the threshold voltage of a corner device  
A structure for increasing the threshold voltage of a corner device, particularly for shallow trench isolation having narrow devices. An FET comprises a substrate having a channel formed therein...
6093953 Isolation regions and methods of forming isolation regions  
A silicon-comprising layer is employed adjacent a trench during planarization of an oxide fill within the trench. An overhanging oxide sidewall is formed along a lateral edge of a trenched...
6091129 Self-aligned trench isolated structure  
A trench-isolated active device and a method of forming a trench-isolated active device on a semiconductor substrate wherein the conductive layer of the device is self-aligned with an isolation...
6087706 Compact transistor structure with adjacent trench isolation and source/drain regions implanted vertically into trench walls  
A semiconductor integrated circuit with a transistor formed within an active area defined by side-walls of a shallow trench isolation region, and method of fabrication thereof, is described. A gate...
6087705 Trench isolation structure partially bound between a pair of low K dielectric structures  
A process is provided for forming dielectric structures having a relatively low dielectric constant arranged adjacent to the opposed lateral edges of a trench isolation structure. In an embodiment,...
6077748 Advanced trench isolation fabrication scheme for precision polysilicon gate control  
An IGFET device isolation structure fabrication scheme includes the formation of electrically insulating isolation structures that extend into the substrate and extend above the surface of the...
6064105 Data retention of EEPROM cell with shallow trench isolation using thicker liner oxide  
A shallow trench isolation structure and a method for forming the same for use with non-volatile memory devices is provided so as to maintain sufficient data retention thereof. An epitaxial layer...
6064104 Trench isolation structures with oxidized silicon regions and method for making the same  
A trench isolation structure in a semiconductor substrate includes a trench opening in the surface of the substrate and a seamless oxide layer filling the trench. The seamless oxide layer is formed...
6054343 Nitride trench fill process for increasing shallow trench isolation (STI) robustness  
A semiconductor device and method having shallow trench isolation. A pad oxide 24 and silicon 42 are formed on a substrate 20 to form a mask, and the pad oxide 24/silicon 42 mask is then patterned....
6051885 Semiconductor device having a conductor with a wedge shaped depression  
A highly integrated semiconductor device is made using a high precision manufacturing process having a comparatively small number of process steps. The device is substantially free of misalignment...
6046483 Planar isolation structure in an integrated circuit  
A method is provided for forming an isolation structure at a semiconducting surface of a body, and the isolation structure formed thereby. A masking layer is formed over selected regions of the...
6046487 Shallow trench isolation with oxide-nitride/oxynitride liner  
Disclosed is an improved process and liner for trench isolation which includes either a single oxynitride layer or a dual oxynitride (or oxide)/nitride layer. Such a process and liner has an...
6040597 Isolation boundaries in flash memory cores  
A wet etching process for establishing isolation grooves in a flash memory core wafer includes depositing nitride and/or oxide layers on a silicon substrate of the wafer, depositing a photoresist...
6040233 Method of making a shallow trench isolation with thin nitride as gate dielectric  
A semiconductor structure comprises a silicon substrate of a first conductivity type including wells of a second conductivity type disposed on a surface thereof and a dielectric layer including...
6034403 High density flat cell mask ROM  
A high-density flat cell mask ROM is disclosed. The mask ROM comprises: a semiconductor substrate having a plurality of trenches and each of the trenches is separated to keep a space with each...
6033941 Method of forming a thin film transistor with asymmetrically arranged gate electrode and offset region  
A thin film transistor which includes an oxide layer containing a trench; a semiconductor layer formed on the oxide layer, including the trench; a buffer layer formed on the semiconductor layer in...
6034393 Nonvolatile semiconductor memory device using trench isolation and manufacturing method thereof  
A nonvolatile semiconductor memory device with trench isolation having sufficient capability of isolating memory cells is provided. A trench formed as a line in the main surface of semiconductor...
6034410 MOSFET structure with planar surface  
A method is provided for a planar surface of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A conductive layer is formed over a substrate. A silicon...
6018180 Transistor formation with LI overetch immunity  
An integrated circuit transistor and a method for making the same are provided. The transistor is resistant to junction shorts due to the overetch of local interconnect trenches. The transistor...
6015985 Deep trench with enhanced sidewall surface area  
The present invention includes a method and system to increase the deep trench sidewall surface area in a storage node on a DRAM chip. By tilting the trenches the capacitance is increased without...
6008521 Integrated circuit employing simultaneously formed isolation and transistor trenches  
A semiconductor fabrication process in which a transistor trench and an isolation trench are simultaneously formed in a semiconductor substrate. The transistor trench is laterally displaced from...
6005279 Trench edge spacer formation  
An insulating trench isolation structure is formed in a semiconductor substrate with a spacer overlying the trench edge to prevent oxide loss during subsequent etching, thereby preventing junction...
5998868 Very dense chip package  
An integrated circuit package or arrangement includes a carrier having a surface topography of projections or recesses for supporting individual semiconductor circuit chips having conversely...
5998848 Depleted poly-silicon edged MOSFET structure and method  
A field effect transistor with reduced corner device problems comprises source and drain regions formed in a substrate, a channel region between the source and drain regions, isolation regions in...
5994756 Substrate having shallow trench isolation  
A semiconductor substrate having a shallow trench isolation (STI) structure and a method of manufacturing the same are provided, i.e., an isolation substrate in which grooves are selectively formed...
5990536 Integrated circuit arrangement having at least two mutually insulated components, and method for its production  
An integrated circuit arrangement having at least two components has in a substrate, an insulation structure (4', 5) between the components which covers at least one side of a trench (3) and is...
5982017 Recessed structure for shallow trench isolation and salicide processes  
A shallow trench isolated FET LDD structure that has a low probability of short circuiting at the silicon to trench interface or between the source or drain and the gate (because of a titanium...
5977609 Method and apparatus for insulating material using trenches  
An island of material has an insulating trench structure. The trench structure includes a first insulating trench surrounded by a second insulating trench. The trenches are joined together by at...
5959322 Isolated SOI memory structure with vertically formed transistor and storage capacitor in a substrate  
A semiconductor device and method for manufacturing the same includes a plurality of memory cells, each cell having a transistor formed on a first semiconductor substrate and comprising first and...
5952707 Shallow trench isolation with thin nitride as gate dielectric  
A semiconductor structure comprises a silicon substrate of a first conductivity type including wells of a second conductivity type disposed on a surface thereof and a dielectric layer including...
5949126 Trench isolation structure employing protective sidewall spacers upon exposed surfaces of the isolation trench  
A shallow trench isolation structure and method for making the same are presented. In an embodiment, a trench dielectric is formed within a shallow trench that is disposed in a semiconductor...
5949125 Semiconductor device having field isolation with a mesa or mesas  
Narrow and wide, planar field isolation region (72, 74, 152, 172, 182) is formed by forming trenches (52, 54) within a substrate (10). For wide, planar field isolation regions (72, 152, 172, 182),...
5945724 Trench isolation region for semiconductor device  
Shallow trench isolation regions in a semiconductor device are formed by utilizing sacrificial spacers such as polysilicon spacers having a rounded shape to form trench isolation areas. The spacer...
5939765 Sidewall profile  
A shallow trench isolation structure and method for forming such structure. In one embodiment, the semiconductor device isolating structure of the present invention includes a trench formed into a...
5925894 Thin film transistor with asymmetrically arranged gate electrode and offset region  
A thin film transistor which includes an oxide layer containing a trench; a semiconductor layer formed on the oxide layer, including the trench; a buffer layer formed on the semiconductor layer in...
5914499 High voltage silicon carbide semiconductor device with bended edge  
The invention relates to a method in which proton or ion implantation is used for restructuring a silicon carbide region from being conductive to being resistive and wherein this implantation...
5903040 Trench isolated integrated circuits including voids  
A trench isolated integrated circuit includes at least one void in the trench at the trench corner. The trench comprises a trench wall, a trench floor and a trench corner between the trench wall...
5886391 Antireflective structure  
Inventive antireflective structures comprise a semiconductor substrate having thereon a combination of a plurality of layers that either that absorb reflected light or that dissipate reflected...
5874769 Mosfet isolation structure with planar surface  
A method is provided for a planar surface of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A conductive layer is formed over a substrate. A silicon...
Matches 401 - 450 out of 574 < 1 2 3 4 5 6 7 8 9 10 11 12 >