Matches 351 - 400 out of 573 < 1 2 3 4 5 6 7 8 9 10 11 12 >
Match Document Document Title
6353254 Device isolation structure and device isolation method for a semiconductor power integrated circuit  
The present invention relates to a device isolation structure and a device isolation method in a semiconductor power IC. The device isolation structure according to the present invention includes:...
6353253 Semiconductor isolation region bounded by a trench and covered with an oxide to improve planarization  
An isolation technique is provided for improving the overall planarity of isolation regions relative to adjacent active area silicon mesas. The isolation process results in a trench formed in field...
6350660 Process for forming a shallow trench isolation  
First of all, a semiconductor substrate that has a pad oxide layer thereon is provided. Then a nitride layer is formed on the pad oxide layer. Next, a photoresist layer is formed and defined on the...
6350659 Process of making semiconductor device having regions of insulating material formed in a semiconductor substrate  
A process for fabricating a silicon-on-insulator integrated circuit in conjunction with a process for shallow trench isolation is disclosed. The shallow trench isolation is performed to define...
6351019 Planarized and fill biased integrated circuit chip  
An isolation and gate planarization method for an integrated circuit chip and chips designed by the method. The method comprises generating a dummy gate conductor (GC) shape and biasing it to the...
6351014 Semiconductor device having different field oxide sizes  
According to a semiconductor device of the present invention, a field oxide film is formed so as to cover the main surface of an SOI layer and to reach the main surface of a buried oxide film. As a...
6348394 Method and device for array threshold voltage control by trapped charge in trench isolation  
A semiconductor device and method of manufacturing thereof are provided. A trench is formed in a semiconductor substrate. A thin oxide liner is preferably formed on surfaces of the trench. A...
6346737 Shallow trench isolation process particularly suited for high voltage circuits  
A process which includes forming trench structures ( 28 ) in a substrate ( 12 ) as part of both the STI isolation structure and the LOCOS/STI isolation structure. Thereafter, a field oxide ( 34 a )...
6337256 Impurity ion segregation precluding layer, fabrication method thereof, isolation structure for semiconductor device using the impurity ion segregation precluding layer and fabricating method thereof  
The present invention relates to the impurity ion segregation precluding layer, the fabrication method thereof, the isolation structure for the semiconductor device using the segregation precluding...
6335556 Semiconductor device and method for manufacturing semiconductor device  
A narrow trench ( 2 ) is formed in a memory circuit region ( 4 ) and a wide trench ( 200 ) is formed in a logic circuit region ( 5 ). An oxide ( 3 B) is formed by CVD to fill the trench ( 2 ) and...
6326283 Trench-diffusion corner rounding in a shallow-trench (STI) process  
An isolation structure on an integrated circuit is formed using a shallow trench isolation process. A layer of buffer oxide is formed on a substrate. A layer of nitride is formed on the layer of...
6326255 Semiconductor device  
A method for manufacturing a semiconductor device includes the steps of (1) forming a pad oxide film of 5 nm or more on a circuit forming surface of a semiconductor substrate; (2) forming an...
6326672 LOCOS fabrication processes and semiconductive material structures  
In one aspect, the invention encompasses a LOCOS process. A pad oxide layer is provided over a silicon-comprising substrate. A silicon nitride layer is provided over the pad oxide layer and...
6323532 Deep divot mask for enhanced buried-channel PFET performance and reliability  
A semiconductor structure comprises first gate conductors which wrap around N-wells of buried-channel P-type metal oxide semiconductor field effect transistors and second gate conductors which do...
6316815 Structure for isolating integrated circuits in semiconductor substrate and method for making it  
A trench isolation structure characterized by a dielectric stud filling and spanning a trench in a semiconductor substrate is suggested for isolating the integrated circuits fabricated in the...
6313008 Method to form a balloon shaped STI using a micro machining technique to remove heavily doped silicon  
The invention describes three embodiments of methods for forming a balloon shaped STI trench. The first embodiment begins by forming a barrier layer over a substrate. An isolation opening is formed...
6313007 Semiconductor device, trench isolation structure and methods of formations  
A trench isolation structure is fabricated using high pressure and low temperature. A substrate is provided within which a trench is formed. The trench walls are annealed in nitrogen at a pressure...
6310384 Low stress semiconductor devices with thermal oxide isolation  
A width of a circuit device isolation region and a width of a device region formed on a semiconductor substrate are determined in such a manner as to satisfy a condition which prevents the...
6294823 Integrated circuit with insulating spacers separating borderless contacts from the well  
An improved integrated circuit and method for making it are described. The integrated circuit includes a shallow trench isolation structure formed adjacent to a well. A borderless contact makes...
6294817 Source/drain-on insulator (S/DOI) field effect transistor using oxidized amorphous silicon and method of fabrication  
Source and drain regions of field effect transistors are fabricated with an electrically insulating layer formed thereunder so as to reduce junction capacitance between each and a semiconductor...
6291870 Semiconductor device  
A semiconductor device is implemented having dummy patterns arranged by designedly determining the ratio of area occupied by a protruded portion of an element formation region considering the...
6288427 Silicon-germanium BiCMOS on SOI  
A BiCMOS integrated circuit is formed with CMOS transistors on an SOI substrate in a silicon layer having a standard thickness of 0.1 μm to 0.2 μm and with Bipolar SiGe transistors formed in an...
6285066 Semiconductor device having field isolation  
Narrow and wide, planar field isolation region (72, 74, 152, 172, 182) is formed by forming trenches (52, 54) within a substrate (10). For wide, planar field isolation regions (72, 152, 172, 182),...
6281557 Read-only memory cell array and method for fabricating it  
A read-only memory cell array has vertical MOS transistors formed on trench walls, and is programmed with a programming mask which covers only the areas at which a transistor is not to be produced....
6281562 Semiconductor device which reduces the minimum distance requirements between active areas  
An isolation which is higher in a stepwise manner than an active area of a silicon substrate is formed. On the active area, an FET including a gate oxide film, a gate electrode, a gate protection...
6268637 Method of making air gap isolation by making a lateral EPI bridge for low K isolation advanced CMOS fabrication  
An isolation structure and a method of making the same are provided. In one aspect, the method includes the steps of forming a trench in a substrate and forming a first insulating sidewall in the...
6268264 Method of forming shallow trench isolation  
A method of fabricating a shallow trench isolation. A trench is formed in a substrate. An insulation plug is formed to fill the trench. The trench has an exposed upper portion above the substrate....
6265754 Covered slit isolation between integrated circuit devices  
A capped slit provides isolation between adjacent devices of an integrated circuit. The cap and slit provide very high immunity to punchthrough and protect the edge of the slit against becoming...
6261920 N-channel MOSFET having STI structure and method for manufacturing the same  
A semiconductor device includes an n-channel MOSFET isolated by an element isolation region of STI structure. A silicon nitride (SiN) region is formed in an Si substrate near the interface between...
6258696 System and method for fabricating semiconductor device and isolation structure thereof  
A method for fabricating a semiconductor device and an isolation structure thereof is disclosed. The isolation structure of a semiconductor device includes a first isolation step for forming a...
6251749 Shallow trench isolation formation with sidewall spacer  
An isolation structure which protrudes above the semiconductor surface and sidewall spacers which smooth the topography over said isolation structure.
6251747 Use of an insulating spacer to prevent threshold voltage roll-off in narrow devices  
A method of forming a semiconductor device minimizes oxide recessing in a trench of a semiconductor device. In one embodiment, forming a nitride spacer surrounding the top trench corner oxide in a...
6239476 Integrated circuit isolation structure employing a protective layer and method for making same  
A method for fabricating an integrated circuit is presented wherein a trench is patterned in a field region of a semiconductor substrate. The trench is defined within the semiconductor substrate by...
6232646 Shallow trench isolation filled with thermal oxide  
A semiconductor apparatus and method for producing shallow trench isolation. The method includes the steps providing a semiconductor substrate member fabricated having a thin barrier oxide layer on...
6229194 Process for filling deep trenches with polysilicon and oxide  
A process for etching and filling a trench prevents the top opening of the trench from being closed off prior to the trench being completely filled. After a masking layer is deposited and...
6218720 Semiconductor topography employing a nitrogenated shallow trench isolation structure  
A method for fabricating an integrated circuit is presented wherein a trench is patterned in a field region of a semiconductor substrate. The trench is defined within the semiconductor substrate by...
6211022 Field leakage by using a thin layer of nitride deposited by chemical vapor deposition  
A nitride layer is deposited over a field oxide layer used to separate transistors formed in a substrate, the nitride layer serving to decrease transistor current leakage. The nitride layer has a...
6208008 Integrated circuits having reduced stress in metallization  
The stresses commonly induced in the dielectrics of integrated circuits manufactured using metal patterning methods, such as reactive ion etching (RIE) and damascene techniques, can be reduced by...
6198150 Integrated circuit with deep trench having multiple slopes  
A quick, deep, clean two step trench process for an SOI/bonded wafer substrate 100 is disclosed. A first isotropic plasma etch using SF6 is made through an opening 40 in the photoresist layer on...
6194772 High-voltage semiconductor device with trench structure  
A structure for high-voltage semiconductor devices that have trench structure, substantially facilitating the integration of the high-voltage devices and the low-voltage devices, is disclosed. The...
6188096 DRAM cell capacitor having increased trench capacitance  
A trench capacitor having an increased surface area. In one embodiment, the trench capacitor is a dual trench capacitor having a first trench and a second trench wherein inner walls of the trenches...
6184566 Method and structure for isolating semiconductor devices after transistor formation  
A method for isolating semiconductor devices comprising providing a semiconductor substrate. The semiconductor substrate includes laterally displaced source/drain regions and channel regions. First...
6180965 Semiconductor device having a static induction in a recessed portion  
In a static induction semiconductor device, particular a high power static induction semiconductor device, recessed portions 12 are formed in one surface of a silicon substrate 11 of one...
6175144 Advanced isolation structure for high density semiconductor devices  
The present invention is directed to a semiconductor device having an improved structure for isolating transistors formed on a semiconductor substrate, and a method for making same. The device is...
6153918 Semiconductor device with improved planarity and reduced parasitic capacitance  
In a semiconductor device and a method of manufacturing the same, a dummy region which can suppress occurrence of a parasitic capacity can be provided for reducing a difference in level without...
6150701 Insulative guard ring for a semiconductor device  
A semiconductor device and fabrication method thereof restrains an amplified current between input voltage Vin and ground voltage Vss, and first and second n-wells are biased into internal voltage...
6150695 Multilevel transistor formation employing a local substrate formed within a shallow trench  
A dual level transistor and a fabrication technique. The dual level transistor is an integrated circuit in which a first transistor is formed on an upper surface of a global dielectric and a second...
6146975 Shallow trench isolation  
The specification describes a dual patterned polish stop layer technique for shallow trench isolation. The shallow trenches are formed by etching trenches in a semiconductor substrate wafer,...
6144086 Structure for improved latch-up using dual depth STI with impurity implant  
A method and structure for improving the latch-up characteristic of semiconductor devices is provided. A dual depth STI is used to isolate the wells from each other. The trench has a first...
6140691 Trench isolation structure having a low K dielectric material isolated from a silicon-based substrate  
A trench isolation structure is provided which includes a dielectric material having a relatively low dielectric constant, K, that is approximately less than 3.8. The capacitance between active...
Matches 351 - 400 out of 573 < 1 2 3 4 5 6 7 8 9 10 11 12 >