Matches 301 - 350 out of 574 < 1 2 3 4 5 6 7 8 9 10 11 12 >
Match Document Document Title
6501148 Trench isolation for semiconductor device with lateral projections above substrate  
A semiconductor device includes a semiconductor substrate in which a trench for element isolation is formed, and an element isolation oxide film buried into the trench in such a manner that the...
6498382 Semiconductor configuration  
The invention relates to a semiconductor configuration in which electrodes are insulated by a gas-filled or evacuated cavity. The semiconductor configuration includes at least two rigid electrodes;...
6495855 Semiconductor device  
A dummy active region is formed in which abrading processes are averaged. A semiconductor device is characterized in that an active region for forming an actual device, a device separation region...
6495900 Insulator for electrical structure  
Structures and methods are disclosed for insulating a polysilicon gate adjacent to an electrically active region with a silicon base layer. A layer of silicon nitride having a thickness in a range...
6486038 Method for and device having STI using partial etch trench bottom liner  
A method of isolation of active islands on a silicon-on-insulator semiconductor device, comprising the steps of (a) providing a silicon-on-insulator semiconductor wafer having a silicon active...
6479880 Floating gate isolation device  
An isolation structure providing electrical isolation in two dimensions between memory cells in semiconductor memory device. The isolation structure comprises a trench formed in a substrate of a...
6479875 Fabrication of semiconductor gettering structures by ion implantation  
The present invention relates to the formation of multiple gettering structures within a semiconductive substrate by ion implantation through recesses in the semiconductive substrate. A preferred...
6476451 Buried guard rings for CMOS device  
A twin-well CMOS integrated circuit device includes an n-well region and a p-well region. Each of the n-well and p-well region includes spaced-apart regions which serve as drain and source regions,...
6472274 MOSFET with self-aligned channel edge implant and method  
A MOSFET device and method, the method involves forming the MOSFET device by selectively doping bordering channel regions in the device such that, in operation, the threshold, or turn-on, voltage...
6469361 Semiconductor wafer  
Techniques for etching a wafer layer using multiple layers of the same photoresistant material and structures formed using such techniques are provided. In a method, first, multiple layers of the...
6465866 Trench isolation regions having trench liners with recessed ends  
A trench isolation structure which prevents a hump phenomenon and an inverse narrow width effect of transistors by rounding the top edges of a trench and increasing the amount of oxidation at the...
6465869 Compensation component and process for producing the compensation component  
A compensation component includes a drift path formed of p-conducting and n-conducting layers which are led around or along a trench. A process for producing the compensation component is also...
6461935 Method of manufacturing trench-shaped isolator  
A semiconductor device having a trench-shaped isolator, adjacent to the semiconductor element region is formed having a width which is continuously decreased in the downward direction for relaxing...
6462419 Semiconductor device and method for manufacturing the same  
A semiconductor element and a circuit thereof are formed on the front surface of a semiconductor substrate of a semiconductor device and are protected with an insulating film. An opening is bored...
6455912 Process for manufacturing shallow trenches filled with dielectric material having low mechanical stress  
This invention provides methods for reducing the mechanical stresses within dielectric layers filling the gaps in shallow trench isolation (STI) regions on semiconductor wafers. The methods include...
6455915 Integrated inductive circuits  
An integrated inductive element may be formed over a substrate. A trench may be defined in a variety of shapes in the substrate beneath the integrated inductive element in order to reduce eddy...
6452246 Semiconductor device having an improved isolation structure, and method of manufacturing the semiconductor device  
A trench is formed on a primary surface of a semiconductor substrate, and is filled with trench material to separate the surface region of the semiconductor substrate into plural active regions. At...
6448630 Semiconductor device comprising a polish preventing pattern  
A semiconductor device having a polish preventing pattern that can improve the planarity of an element formation region after the CMP method polishing is provided. To the shape of an element...
6448606 Semiconductor with increased gate coupling coefficient  
A reduced device geometry semiconductor memory device is provided which has increased device efficiency because of an increased gate coupling coefficient. Shallow trench isolations are formed in a...
6445048 Semiconductor configuration having trenches for isolating doped regions  
A semiconductor configuration includes a substrate having a first conduction type. A transistor configuration is disposed at the substrate and is formed from at least one field-effect transistor...
6445044 Apparatus improving latchup immunity in a dual-polysilicon gate  
The invention is a method for creating a portion of an integrated circuit on a semiconductor wafer. The invention comprises doping a substrate to form a doped well region having an opposite...
6445043 Isolated regions in an integrated circuit  
A process for forming isolated active device regions on a silicon substrate comprises the steps of forming at least one trench in a silicon substrate to define at least two active device regions on...
6439514 Semiconductor device with elements surrounded by trenches  
Pch-MOS transistors to which a power supply potential is applied are respectively surrounded by first trenches, and Nch-MOS transistors to which a ground potential is applied are respectively...
6441444 Semiconductor device having a nitride barrier for preventing formation of structural defects  
Providing a method of producing a semiconductor device and a structure of the semiconductor device employing a trench isolation structure for isolating semiconductor elements wherein volumetric...
6433401 Microfabricated structures with trench-isolation using bonded-substrates and cavities  
A microstructure and method for forming the microstructure are disclosed. The method includes: providing a handle substrate; providing a device substrate in which high-aspect-ratio structures and...
6429091 Patterned buried insulator  
A patterned buried insulator is formed beneath the source and drain by forming a mask over the body area and implanting a dose of n or p type ions in the areas where the source and drains will be...
6429502 Multi-chambered trench isolated guard ring region for providing RF isolation  
A novel trench isolated guard ring region for providing RF isolation is disclosed. The semiconductor integrated circuit (IC) device of the present invention comprises a substrate, an insulating...
6420749 Trench field shield in trench isolation  
A method and structure for a semiconductor device which includes a substrate comprising trenches, a plurality of devices on the substrate isolated by the trenches, conductive sidewall spacers...
6414364 Isolation structure and process therefor  
A novel shallow-trench isolation (STI) structure and process for forming it is described. More particularly, a recess is formed in a semiconductor substrate. An oxide layer is formed in the recess...
6413836 Method of making isolation trench  
A method of making an isolation trench structure in a semiconductor substrate is disclosed. A first layer is formed on a semiconductor substrate. The first layer is subsequently patterned to form...
6414361 Buried shallow trench isolation and method for forming the same  
An integrated semiconductor device includes a substrate having a buried shallow trench isolation structure and an epitaxial layer disposed over the substrate and the buried shallow trench isolation...
6404011 Semiconductor power integrated circuit  
A method for fabricating a semiconductor power integrated circuit includes the steps of forming a semiconductor structure having at least one active region, wherein an active region includes a well...
6404020 Method of forming contact pads in a semiconductor device and a semiconductor device formed using the method  
A semiconductor device having a self-aligned contact pad and the method for manufacturing the device are disclosed. The semiconductor device includes: an isolation region formed in a semiconductor...
6399461 Addition of planarizing dielectric layer to reduce a dishing phenomena experienced during a chemical mechanical procedure used in the formation of shallow trench isolation regions  
A process for fabricating silicon oxide filled, shallow trench isolation (STI), regions, in a semiconductor substrate, featuring the use of a disposable boro-phosphosilicate glass (BPSG), layer,...
6396090 Trench MOS device and termination structure  
A termination structure for power trench MOS devices is disclosed. The MOS devices can be Schottky diode, IGBT or DMOS depending on what kinds of the semiconductor substrate are prepared. The...
6391739 Process of eliminating a shallow trench isolation divot  
A process of fabricating a shallow trench isolation structure includes the steps of: providing a substrate; forming a first insulating layer over the substrate; forming a nitride masking layer over...
6392269 Non-volatile semiconductor memory and manufacturing method thereof  
A non-volatile semiconductor memory manufacturing method, according to the present invention, is comprised of the process steps that follow. Device isolating layers are formed on predetermined...
6388304 Semiconductor device having buried-type element isolation structure and method of manufacturing the same  
The present invention is a semiconductor device having an element isolation structure of STI, in which after the formation of the STI trench, a silicon nitride film is left over only on the side...
6388303 Semiconductor device and semiconductor device manufacture method  
There is disclosed a semiconductor device in which trenches are formed at predetermined intervals on a silicon substrate. In each trench, a first silicon oxide film is formed with the upper region...
6380606 Locos isolation process using a layered pad nitride and dry field oxidation stack and semiconductor device employing the same  
The present invention provides methods of manufacturing a field oxide isolation structure over a semiconductor. One of the methods includes the steps of: (1) depositing a first stack-nitride...
6380599 Method and apparatus for trench isolation process with pad gate and trench edge spacer elimination  
A microelectronic device includes a field oxide isolation pad which extends from a trench formed in a microelectronic substrate by a height which is less than approximately two times the height of...
6376877 Double self-aligning shallow trench isolation semiconductor and manufacturing method therefor  
A reduced device geometry and increased device efficiency semiconductor memory device is provided. The method of manufacturing the semiconductor memory device includes forming shallow trench...
6372604 Method for forming a trench type element isolation structure and trench type element isolation structure  
There is provided a method for forming a trench type element isolation structure wherein no recess develops in the edge part of an imbedded oxide film of a trench type element isolation. Thermal...
6372605 Additional etching to decrease polishing time for shallow-trench isolation in semiconductor processing  
During formation of shallow-trench isolation (STI) structures during semiconductor processing, an additional oxide-reduction etching step is performed prior to chemical-mechanical processing. In...
6368941 Fabrication of a shallow trench isolation by plasma oxidation  
The present invention provides a method of fabricating a STI on a wafer to eliminate the common occurrence of junction leakage in the prior art. The method begins by forming a patterned hard mask...
6365952 Trench isolation for CMOS devices  
The present invention is an isolation trench with an insulator, and a method of forming the same using self-aligned processing techniques. The method is implemented with a single mask. A shallow...
6365953 Wafer trench article and process  
A bonded wafer 100 has a device substrate 16 with isolation trenches 30 defining device regions 18. Oxide dogbone structures are removed before filling trenches 30. Voids 36 in the...
6359299 Apparatus and method for forming controlled deep trench top isolation layers  
A method for controlling isolation layer thickness in deep trenches for semiconductor memories in accordance with the present invention includes the steps of providing a deep trench having a...
6355538 Method of forming isolation material with edge extension structure  
A method of forming an isolation trench structure wherein the dielectric material filling the trench extends beyond the trench edges thereby preventing gaps at the trench edges. A layer of first...
6355539 Method for forming shallow trench isolation  
A method for forming a shallow trench isolation is disclosed. The method avoids using any silicon nitride material to prevent the kooi effect and use spacers to protect the corner portions of the...
Matches 301 - 350 out of 574 < 1 2 3 4 5 6 7 8 9 10 11 12 >