Matches 251 - 300 out of 574 < 1 2 3 4 5 6 7 8 9 10 11 12 >
Match Document Document Title
6710421 Semiconductor devices and methods for manufacturing the same  
A semiconductor device may include a first wiring layer 30 , an interlayer dielectric layer 40 formed above the first wiring layer 30 , a second wiring layer 50 formed above the interlayer...
6710401 Semiconductor device including a trench with at least one of an edge of an opening and a bottom surface being round  
A semiconductor device which includes a substrate made of a semiconductor having a main surface. A trench is selectively formed in the substrate at a predetermined depth from the main surface. An...
6700158 Trench corner protection for trench MOSFET  
A method of making a trench MOSFET structure having upper trench corner protection, the method not requiring trench corner rounding or sacrificial oxide/strip steps. The trench MOSFET structure...
6696742 Semiconductor memory device  
A semiconductor memory device includes a semiconductor substrate having a first conductivity type and multiple parallel trenches extending in a first direction in the substrate. Each trench is...
6696743 Semiconductor transistor having gate electrode and/or gate wiring  
A semiconductor transistor formed between trench device isolation regions comprises; a gate electrode formed on a device formation region with the intervention of a gate insulating film and...
6689665 Method of forming an STI feature while avoiding or reducing divot formation  
A method for forming shallow trench isolation (STI) features to reduce or avoid divot formation at STI trench corners including providing a shallow trench isolation (STI) feature included in a...
6686645 Fuse and fuse window structure  
A fuse structure. A first dielectric layer is formed on a substrate, a first conductive layer is formed on part of the first dielectric layer, a second dielectric layer is formed on part of the...
6683364 Integrated circuit devices including an isolation region defining an active region area and methods for manufacturing the same  
Integrated circuit devices including an isolation region are provided. The devices include an integrated circuit substrate and a trench in the integrated circuit substrate that defines an active...
6677659 Method for fabricating 3-dimensional solenoid and device fabricated  
A method for fabricating a 3-dimensional solenoid utilizing a CMOS fabrication technology and a back end process without using photomasking is described. In the method, two suspended arms each...
6674134 Structure and method for dual gate oxidation for CMOS technology  
The present invention provides an integrated circuit which comprises a substrate having a plurality of device regions formed therein, said plurality of device regions being electrically isolated...
6670672 Structure of discrete NROM cell  
A discrete NROM cell, at least comprising: a substrate; a first ON stacking gate and a second ON stacking gate over the substrate, wherein the ON stacking gate is a structure having a nitride layer...
6670691 Shallow trench isolation fill process  
A method for filling narrow isolation trenches during a semiconductor fabrication process is disclosed. The semiconductor includes both high-aspect ratio narrow isolation trenches formed in a core...
6661065 Semiconductor device and SOI substrate  
A systematized semiconductor device having a gate insulating film which can be formed thinner than a silicon oxide film and which is less susceptible to deterioration. Further, a semiconductor...
6645825 Planarization of shallow trench isolation (STI)  
An improved and new process for fabricating a planarized structure of shallow trench isolation (STI) embedded in a silicon substrate has been developed. The planarizing method comprises a two-step...
RE38296 Semiconductor memory device with recessed array region  
A semiconductor memory wherein a memory cell region having a plurality of memory cells and a relatively high altitude above the surface of semiconductor substrate is formed at a recessed part of...
6635946 Semiconductor device with trench isolation structure  
A semiconductor device with trench isolation structure is disclosed. The invention uses a trench isolation structure that can be formed by using conventional methods to prevent problems such as...
6635945 Semiconductor device having element isolation structure  
A semiconductor device and process of forming the device are described. The process includes forming a pad oxide film on the circuit-forming side of a semiconductor substrate; forming an oxidation...
6624496 Method of forming T-shaped isolation layer, method of forming elevated salicide source/drain region using the same, and semiconductor device having T-shaped isolation layer  
A method of forming a T-shaped isolation layer, a method of forming an elevated salicide source/drain region using the same, and a semiconductor device having the T-shaped isolation layer are...
6624475 SOI low capacitance body contact  
An FET device and method of making comprising a first dielectric layer; a substrate layer on the dielectric layer; a channel region of a first conductivity type formed in the substrate layer; a...
6621136 Semiconductor device having regions of low substrate capacitance  
A semiconductor device ( 10 ) includes an electrical component ( 70 ) formed on a dielectric region ( 22 ) of a semiconductor substrate ( 12 ). The dielectric region is formed with a first...
6617663 Methods of manufacturing semiconductor devices  
A planarization method includes forming a dummy pattern in a film over a substrate. The dummy pattern includes a plurality of concave and convex portions. A chemical-mechanical polishing process is...
6617646 Reduced substrate capacitance high performance SOI process  
A silicon on insulator substrate is provided to include the following: a handle wafer; a layer of bonding material; a device wafer, the device wafer including at least one buried impurity region...
6613645 Method of manufacturing semiconductor device with glue layer in opening  
The present invention provides a structure in which a glue layer is formed on an active area and a shallow trench isolation with a glue layer interposed therebetween. A P-type silicon substrate...
6614094 High integration density vertical capacitor structure and fabrication process  
A vertical capacitor structure fabricated in a semiconductor substrate region overlaid by a buried oxide layer and a buried doped layer, as well as by a semiconductor layer that includes a sinker...
6614062 Semiconductor tiling structure and method of formation  
A semiconductor device and method of fabrication are disclosed. The device includes a first trench isolation region having an allowable tiling area and a second trench isolation region having an...
6611059 Integrated circuitry conductive lines  
Integrated circuitry includes a semiconductive substrate, an insulative material over the semiconductive substrate, and a series of alternating first and second conductive lines, the first and...
6605855 CVD plasma process to fill contact hole in damascene process  
The present invention relates to a method for fabricating interconnecting lines and vias in a layer of insulating material. A via is formed in the layer of insulating material. A protective...
6597026 Semiconductor device comprising plural isolated channels in a shallow trench isolation region  
A semiconductor device includes a plurality of shallow trench isolation bands, a plurality of channels, a source electrode, a drain electrode, and a gate electrode. The shallow trench isolation...
6596607 Method of forming a trench type isolation layer  
A method of forming a trench type isolation layer is provide, wherein the method comprises: forming a trench by etching after forming a trench etching pattern on a substrate; forming a silicon...
6593637 Method for establishing component isolation regions in SOI semiconductor device  
A method for making an SOI semiconductor device including a silicon substrate includes implanting oxide and Nitrogen into the substrate and then annealing to drive Oxygen and Nitrogen through and...
6590271 Extension of shallow trench isolation by ion implantation  
A shallow trench isolation (STI) structure is formed by etching trenches into the surface of a substrate in alignment with a patterned masking layer. An ion implantation of, for example, carbon,...
6586814 Etch resistant shallow trench isolation in a semiconductor wafer  
A shallow isolating trench is formed in a semiconductor wafer between active component areas to electrically isolate the active components from each other. The isolating trench is primarily formed...
6583489 Method for forming interconnect structure with low dielectric constant  
The present invention provides a method for forming low dielectric constant inter-metal dielectric layer. The method comprises providing a semiconductor substrate and forming a first dielectric...
6583488 Low density, tensile stress reducing material for STI trench fill  
A method of isolation of active regions on a silicon-on-insulator semiconductor device, including the steps of: providing a silicon-on-insulator semiconductor wafer having a silicon active layer,...
6576345 Dielectric films with low dielectric constants  
Thin films possessing low dielectric constants (e.g., dielectric constants below 3.0) are formed on integrated circuits or other substrates. Caged-siloxane precursors are linked in such a way as to...
6573152 Self-planarizing process for shallow trench isolation  
Described is a method to form isolation structures on a semiconductor substrate. This method begins with forming one or more trenches in the semiconductor substrate and depositing a first portion...
6566225 Formation method of shallow trench isolation  
The present invention provides a formation method of a trench structure comprising forming a pad oxide layer on a substrate. A first polysilicon layer is formed on the pad oxide layer and an oxide...
6566226 Semiconductor device and fabrication process thereof, method of forming a device isolation structure  
In a semiconductor device having an STI structure, a space is formed by causing a recession in an oxide film on a surface of a substrate with regard to a sidewall surface of a device isolation...
6559028 Method of topography management in semiconductor formation  
The method as disclosed reduces the topological step between the uppermost surface of a substrate and the uppermost surface of a shallow trench isolation feature. The method includes the steps of...
6552408 Methods, apparatuses, and substrate assembly structures for fabricating microelectronic components using mechanical and chemical-mechanical planarization processes  
Methods, apparatuses and substrate assembly structures for mechanical and chemical-mechanical planarizing processes used in the manufacturing microelectronic-device substrate assemblies. One aspect...
6552407 Communication module having a structure for reducing crosstalk  
Disclosed herein is a communication module, comprising a semiconductor chip in which channels for allowing signal converting means to convert current signals inputted from input terminals to...
6541861 Semiconductor device manufacturing method including forming step of SOI structure and semiconductor device having SOI structure  
A semiconductor manufacturing method has the steps of preparing an SOI substrate having a supporting substrate, an insulating film formed above the supporting substrate, a semiconductor region...
6534840 Semiconductor device having self-aligned structure  
A sidewall insulating film is formed on the side faces of a gate electrode on a substrate. A trench isolation film is also formed to be self-aligned with the gate electrode. The upper surface of...
6525360 Semiconductor device using a shallow trench isolation  
In a MOS transistor using shallow trench isolation, a pattern of an element formation region has a shape of a modified hexagon in which a hexagon is compressed into a shape like a rhombus in a...
6525403 Semiconductor device having MIS field effect transistors or three-dimensional structure  
A semiconductor projection is formed on a semiconductor substrate of the first conductivity type and has a semiconductor layer of the first conductivity type. The semiconductor projection has a top...
6518641 Deep slit isolation with controlled void  
An isolation region for a memory array in which the isolation region includes at least one trench region having sidewalls that extend to a bottom surface and a slit region formed beneath the final...
6515351 Integrated circuit with borderless contacts  
An integrated circuit comprising a conductive region formed on a semiconductor substrate, a silicate glass layer formed on the conductive region, and an etch stop layer formed on the silicate glass...
6514885 Semiconductor device manufacturing method to reduce process induced stress and crystalline defects  
To reduce dislocations produced in the formation of shallow trench isolation regions in a semiconductor substrate, the semiconductor substrate is annealed in N 2 ambient pressure with an O 2 ...
6512282 Semiconductor device and method for fabricating the same  
A sidewall insulating film is formed on the side faces of a buried gate electrode on a substrate. A trench isolation film, self-aligned with the gate electrode, is also formed so that the upper...
6504216 Electrostatic discharge protective circuit  
An electrostatic discharge protective circuit. The electrostatic discharge protective circuit includes a gate electrode. A drain is formed at one side of the gate electrode. A source is formed at...
Matches 251 - 300 out of 574 < 1 2 3 4 5 6 7 8 9 10 11 12 >