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7253493 High density access transistor having increased channel width and methods of fabricating such devices  
A memory device having decreased cell size and having transistors with increased channel widths. More specifically, pillars are formed in a substrate such that sidewalls are exposed. The sidewalls...
7242071 Semiconductor structure  
A structure comprises a deep sub-collector buried in a first epitaxial layer and a near sub-collector buried in a second epitaxial layer. The structure further comprises a deep trench isolation...
7238564 Method of forming a shallow trench isolation structure  
A method and system for isolation trenches includes forming isolation trenches in a semiconductor substrate, filling the trenches with a filler material, creating voids near top edges of the...
7235856 Trench isolation for semiconductor devices  
In etching trench isolation structures, a pad oxide or sacrificial oxide may be formed with substantially the same (or higher) etch rate as the trench filler. Because the etch rate in the trench...
7235857 Power semiconductor device  
A semiconductor device is provided in which a plurality of MOSFETs including a vertical MOSFET is formed on a substrate. The device includes a silicon carbide substrate having front and back...
7233046 Semiconductor device and fabrication method thereof  
A semiconductor device and fabrication method thereof restrains an amplified current between input voltage Vin and ground voltage Vss, and first and second n-wells are biased into internal voltage...
7230312 Transistor having vertical junction edge and method of manufacturing the same  
Techniques for forming devices, such as transistors, having vertical junction edges. More specifically, shallow trenches are formed in a substrate and filled with an oxide. Cavities may be formed...
7224038 Semiconductor device having element isolation trench and method of fabricating the same  
A semiconductor device capable of preventing defective embedding of an insulator and improving the withstand voltage (dielectric strength) of an element isolation region is obtained. This...
7208754 Strained silicon structure  
A semiconductor device includes a substrate, a first epitaxial layer, a second epitaxial layer, a third epitaxial layer, a first trench, and a second trench. The first epitaxial layer is formed on...
7208812 Semiconductor device having STI without divot and its manufacture  
The method of manufacturing a semiconductor device has the steps of: etching a semiconductor substrate to form an isolation trench by using as a mask a pattern including a first silicon nitride...
7199411 Solid-state imaging device and camera  
A solid-state imaging device is formed on a silicon substrate for providing a MOS type solid-state imaging device which has a device isolation structure and causes a small amount of leak current....
7196381 Corner protection to reduce wrap around  
A method and structure are provided with reduced gate wrap around to advantageously control for threshold voltage and increase stability in semiconductor devices. A spacer is provided aligned to...
7196394 Method and apparatus for a deposited fill layer  
A method of forming a semiconducting wafer is provided that utilizes fewer processing operations, reduces process variation, and lowers cost as well as production time. The method provided further...
7193269 MOS semiconductor device  
While using conventional manufacturing processes, it is intended to apply a compressive strain in the channel direction to the p-channel MOS field effect transistor and also apply a tensile strain...
7190042 Self-aligned STI for narrow trenches  
A self-aligned shallow trench isolation region for a memory cell array is formed by etching a plurality of vertical deep trenches in a substrate and coating the trenches with an oxidation barrier...
7186609 Method of fabricating trench junction barrier rectifier  
A Schottky rectifier includes a rectifying interface between a semiconductor body and a metal layer. Trenches are formed in the surface of the semiconductor body and regions of a conductivity type...
7176549 Shallow trench isolation using low dielectric constant insulator  
A shallow trench isolation is disclosed wherein the trench depth is reduced beyond that achieved in prior art processes. The reduced trench depth helps to eliminate the formation of voids during...
7170156 Laminar multi-layer piezoelectric roll component  
A multi-layer piezoelectric component includes a plurality of piezoelectric layers, a first inner electrode sheet, a second inner electrode sheet, a first outer electrode, and a second outer...
7170109 Heterojunction semiconductor device with element isolation structure  
A technique enabling to improve element isolation characteristic of a semiconductor device is provided. An element isolation structure is provided in a semiconductor substrate in which a silicon...
7166901 Semiconductor device  
A semiconductor device comprises a semiconductor substrate having a high voltage region and a low voltage region, at least a pair of adjacent high voltage MOS transistors disposed on the high...
7157770 MOS transistor with recessed gate and method of fabricating the same  
A MOS transistor with a recessed gate and a method of fabricating the same: The MOS transistor comprises a semiconductor substrate, and a trench isolation layer located in a predetermined region of...
7151023 Metal gate MOSFET by full semiconductor metal alloy conversion  
A MOSFET structure and method of forming is described. The method includes forming a metal-containing layer that is thick enough to fully convert the semiconductor gate stack to a semiconductor...
7138319 Deep trench isolation of embedded DRAM for improved latch-up immunity  
A protective structure for blocking the propagation of defects generated in a semiconductor device is disclosed. In an exemplary embodiment, the structure includes a deep trench isolation formed...
7129559 High voltage semiconductor device utilizing a deep trench structure  
A semiconductor device includes a substrate having a source, a drain, and a gate between the source and the drain. Both the source and the drain include a first edge, and the gate includes a first...
7122876 Isolation-region configuration for integrated-circuit transistor  
A transistor of an integrated circuit is provided. A first doped well region is formed in a well layer at a first active region. At least part of the first doped well region is adjacent to a gate...
7122866 Semiconductor memory device with a stacked gate including a floating gate and a control gate and method of manufacturing the same  
A semiconductor memory device includes first and second MOS transistors. The first MOS transistor is formed on a region enclosed by a first element isolating region and includes a first gate...
7122416 Method for forming a filled trench in a semiconductor layer of a semiconductor substrate, and a semiconductor substrate with a semiconductor layer having a filled trench therein  
A method for forming an isolation filled trench ( 25 ) in a silicon layer ( 21 ) of an SOI structure ( 20 ). The trench ( 25 ) is relieved adjacent its open mouth ( 30 ) in order to displace the...
7119386 Versatile system for triple-gated transistors with engineered corners  
The present invention provides a system for producing a triple-gate transistor segment ( 300 ), utilizing a standard semiconductor substrate ( 302 ). The substrate has a plurality of isolation...
7118942 Method of making atomic integrated circuit device  
A method of mass-producing a solid state device comprises providing an atomically smooth, solid state material layer no more than 40 Angstroms thick. This layer is uniformly and defect-freely...
7119412 Semiconductor device and method for manufacturing the same  
After formation of a gate insulating film for a high voltage transistor on the entire surface, when removing the gate insulating film existing within a low voltage region, etching is not finished...
7112849 Method of preventing semiconductor layers from bending and semiconductor device formed thereby  
Disclosed herein are various methods for preventing bending of a patterned SOI layer during trench sidewall oxidation, the methods comprising providing a patterned SOI layer having at least one...
7109551 Semiconductor device  
A semiconductor structure with device trench and a semiconductor device in the device trench, that enables realization of high integration, lowered on-resistance, reduction in switching losses and...
7105908 SRAM cell having stepped boundary regions and methods of fabrication  
A semiconductor device comprises a substrate. In addition, the semiconductor device comprises an active region and an isolation region. The active region is in the substrate and comprises a...
7102167 Method and system for providing a CMOS output stage utilizing a buried power buss  
A CMOS output stage is disclosed. The CMOS output stage comprises a substrate and at least one well coupled to the substrate. The CMOS output stage also includes a plurality of slots provided...
7095081 Semiconductor device and manufacturing method thereof  
A semiconductor device includes a substrate having first to fourth regions, a first insulating film formed on the substrate in the first region, a first epitaxial layer formed on the substrate in...
7095093 Semiconductor device and method of manufacturing a semiconductor device  
A semiconductor device comprises a semiconductor substrate having a substrate top surface on which a device should be formed; a gate electrode having an opposed surface opposed to said substrate...
7091536 Isolation process and structure for CMOS imagers  
A barrier implanted region of a first conductivity type located below an isolation region of a pixel sensor cell and spaced from a doped region of a second conductivity type of a photodiode of the...
7091574 Voltage island circuit placement  
A voltage island is disclosed. The voltage island comprises a physical domain and a lower voltage supply rail within the physical domain. The voltage island also includes an upper voltage supply...
7084477 Semiconductor device and manufacturing method of the same  
To suppress defects occurred in a semiconductor substrate, a semiconductor device is constituted by having: the semiconductor substrate; an element isolating region having a trench formed in the...
7075151 Semiconductor memory device for storing data as state of majority carriers accumulated in channel body and method of manufacturing the same  
A semiconductor memory device comprises a substrate; a first semiconductor layer of a first conduction type having a single crystalline structure isolated from the substrate by an insulator layer;...
7071529 Semiconductor device having a Damascene gate or a replacing gate  
A semiconductor device includes semiconductor elements and at least one dummy pattern. Each or at least some of the semiconductor elements has a Damascene gate structure or a replacing gate...
7071515 Narrow width effect improvement with photoresist plug process and STI corner ion implantation  
A method to reduce the inverse narrow width effect in NMOS transistors is described. An oxide liner is deposited in a shallow trench that is formed to isolate active areas in a substrate. A...
7067890 Thick oxide region in a semiconductor device  
A method of forming an oxide region in a semiconductor device includes the steps of forming a plurality of trenches in a semiconductor layer of the device, the trenches being formed in close...
7061069 Semiconductor device having two-layered charge storage electrode  
A first insulation film, a first conductor film, and a cap are sequentially formed on a semiconductor substrate. The first insulation film, the first conductor film, and the cap, and the substrate...
7061041 Memory device  
A memory device is provided. The memory device comprises a substrate, first isolation structures, stacked device structures, and second isolation structures. The substrate comprises a memory cell...
7061068 Shallow trench isolation structures having uniform and smooth topography  
Ions are implanted into the dielectric layer and/or barrier layer over a semiconductor substrate to change the polish rates of either or both layers during formation of a shallow trench isolation...
7056795 Thin-film transistor used as heating element for microreaction chamber  
The thin film transistor formed of polycrystalline silicon is positioned adjacent a heat reaction chamber. The gate electrode for the transistor is formed within a silicon substrate and a gate...
7057257 Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry  
Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry are described. In one...
7057242 Transistor structures having access gates with narrowed central portions  
An integrated circuit transistor includes an active region in a substrate, elongated along a first direction. A gate pattern is disposed on the substrate and crosses the active region along a...
7053451 Semiconductor device having impurity region under isolation region  
In formation of a source/drain region of an NMOS transistor, a gate-directional extension region < 41 a > of an N + block region < 41 > in an N + block resist film < 51 >...