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8183549 Substrate holding apparatus, and inspection or processing apparatus  
In order to enable high accuracy positioning and strong pressing of a substrate, the present invention provides a substrate holding apparatus including: a rotating bed having an inclined surface...
8183691 Semiconductor device with pads overlapping wiring layers including dummy wiring  
A semiconductor device includes plural electrode pads arranged in an active region of a semiconductor chip, and wiring layers provided below the plural electrode pads wherein occupation rates of...
8183565 Programmable resistance memory array with dedicated test cell  
A rewritable nonvolatile memory includes a test cell that is dedicated to testing the storage characteristics of other, similar, storage cells formed within the same integrated circuit memory. The...
8178364 Testing method of surface-emitting laser device and testing device thereof  
A method of performing a wafer level burn-in test for a plurality of surface-emitting laser devices formed on a wafer includes causing a plurality of contact electrodes arranged in a same plane...
8178942 Electrically alterable circuit for use in an integrated circuit device  
An electrically alterable circuit (EAC), suitable for use in an integrated circuit, includes a first interconnect, a link element, and a second interconnect. A first set of interconnect vias...
8178876 Method and configuration for connecting test structures or line arrays for monitoring integrated circuit manufacturing  
A test chip comprises at least one level having an array of regions. Each region is capable of including at least one test structure. At least some of the regions include respective test...
8174010 Unified test structure for stress migration tests  
A unified test structure which is applicable for all levels of a semiconductor device including a current path chain having a first half chain and a second half chain, wherein each half chain...
8174011 Positional offset measurement pattern unit featuring via-plug and interconnections, and method using such positional offset measurement pattern unit  
In a positional offset measurement pattern unit formed in an insulating layer, a first interconnection is formed in the insulating layer. A via-plug is formed in the insulating layer so as to be...
8174282 Leak current detection circuit, body bias control circuit, semiconductor device, and semiconductor device testing method  
A leak current detection circuit that improves the accuracy for detecting a leak current in a MOS transistor without enlarging the circuit scale. The leak current detection circuit includes at...
8173449 Method for making COP evaluation on single-crystal silicon wafer  
An evaluation area of an evaluation object wafer is concentrically divided in a radial direction, an upper limit value to the number of COPs is set in each divided evaluation segment, and an...
8169230 Semiconductor device and method of testing the same  
A semiconductor device is formed on a semiconductor wafer. The semiconductor device has: an output buffer configured to externally output an output signal received from an internal circuit; an...
8168970 Die having embedded circuitry with test and test enable circuitry  
Timely testing of die on wafer reduces the cost to manufacture ICs. This disclosure describes a die test structure and process to reduce test time by adding test pads on the top surface of the die....
8168452 Method for manufacturing semiconductor device  
A method for manufacturing a semiconductor device, the semiconductor device including an integrated circuit having plural connection terminals arranged on a predetermined local region of the...
8163574 System and method for sensing voltage in medium-to-high voltage applications  
A system and method for measuring voltage of a medium to high voltage line conductor is disclosed. The system includes an electrical insulator having a surface and an edge, the surface having an...
8164091 Multi-purpose poly edge test structure  
Multi-purpose poly edge test structure. According to an embodiment, the present invention provides a test structure. The test structure includes a doped silicon substrate, the doped silicon...
8159254 Crack sensors for semiconductor devices  
Crack sensors for semiconductor devices, semiconductor devices, methods of manufacturing semiconductor devices, and methods of testing semiconductor devices are disclosed. In one embodiment, a...
8159252 Test handler and method for operating the same for testing semiconductor devices  
A test handler and method for operating a test handler for testing semiconductor devices are provided. The test handler includes a test tray located on one side of an opening apparatus in which a...
8154019 Semiconductor apparatus and calibration method thereof  
A semiconductor apparatus includes a reference voltage generation unit, a comparison voltage generation unit, and a calibration unit. The reference voltage generation unit is disposed in a...
8149152 Capacitor based digital to analog converter layout design for high speed analog to digital converter  
A method and system for capacitor based digital to analog converter design layout for high speed analog to digital converter are provided. The method includes arranging a plurality of metal plates...
8143705 Tamper-resistant semiconductor device and methods of manufacturing thereof  
The invention relates to a tamper-resistant semiconductor device comprising a substrate (5) comprising an electronic circuit arranged on a first side thereof. An electrically-conductive protection...
8143619 Methods of combinatorial processing for screening multiple samples on a semiconductor substrate  
In embodiments of the current invention, methods of combinatorial processing and a test chip for use in these methods are described. These methods and test chips enable the efficient development of...
8143098 Integrated circuit packaging system with interposer and method of manufacture thereof  
A method of manufacture of an integrated circuit packaging system includes: providing an interposer having device contacts, interconnect contacts, and test pads including the interconnect contacts...
8145959 Systems and methods for measuring soft errors and soft error rates in an application specific integrated circuit  
A test system includes a computer and an interface device for accessing a scan chain on an application specific integrated circuit (ASIC) under test. The computer includes a memory that contains...
8142966 Substrate matrix to decouple tool and process effects  
A method of characterizing a process by selecting the process to characterize, selecting a parameter of the process to characterize, determining values of the parameter to use in a test matrix,...
8138497 Test structure for detecting via contact shorting in shallow trench isolation regions  
A test structure for detecting void formation in semiconductor device layers includes a plurality of active device areas formed in a substrate, a plurality of shallow trench isolation (STI) regions...
8138498 Apparatus and methods for determining overlay of structures having rotational or mirror symmetry  
Disclosed are overlay targets having flexible symmetry characteristics and metrology techniques for measuring the overlay error between two or more successive layers of such targets. Techniques for...
8134187 Integrated mask-programmable logic devices with multiple metal levels and manufacturing process thereof  
Integrated mask-programmable device, having a plurality of metal levels including a top metal level, a bottom metal level and a first intermediate metal level formed between the top and bottom...
8124428 Structure and method for testing MEMS devices  
A method for determining the presence of a sacrificial layer under a structure. The method includes providing at least one structure arranged above a substrate having a major surface lying in a...
8125796 Devices with faraday cages and internal flexibility sipes  
A computer or microchip comprising an outer chamber and at least one inner chamber inside the outer chamber. The outer chamber and the inner chamber being separated at least in part by an internal...
8120024 Semiconductor package having test pads on top and bottom substrate surfaces and method of testing same  
A semiconductor package and testing method is disclosed. The package includes a substrate having top and bottom surfaces, a semiconductor chip mounted in a centrally located semiconductor chip...
8120026 Testing wiring structure and method for forming the same  
The invention provides a testing wiring structure of a thin film transistor (TFT) motherboard for applying signals to a plurality of signal lines in a pixel region on the motherboard and a method...
8115202 Thin film transistor array substrate and electronic ink display device  
A thin film transistor array substrate suitable for being applied in an electronic ink display device is provided. The thin film transistor array substrate includes a substrate, scan lines, data...
8110926 Redistribution layer power grid  
An integrated circuit package including a first metal layer coupled to a bonding pad, a first redistribution layer coupled to the bonding pad, and a RDL to Metal (RTM) via coupled to a first...
8110905 Integrated circuit packaging system with leadframe interposer and method of manufacture thereof  
A method of manufacture of an integrated circuit packaging system includes: forming a substrate; mounting a base integrated circuit on the substrate; forming a leadframe interposer, over the base...
8110852 Semiconductor integrated circuit device  
A finger length a1 of a transistor P11 is longer than a finger length A1 of a transistor P1, and a finger length b1 of a transistor N11 is longer than a finger length B1 of a transistor N1. The...
8106654 Magnetic sensor integrated circuit device and method  
An sensor includes a substrate with a magnetic field sensor mounted on the substrate. The magnetic field sensor has a first surface defining a plane. A magnetic flux conducting member has a second...
8106395 Semiconductor device and method of manufacturing the same  
A technique of manufacturing a semiconductor device capable of performing a probe test by a common test apparatus as normal LSI chips even for large-area chips is provided. A chip comprising a...
8106396 Thin film transistor array substrate  
A thin film transistor array substrate includes a substrate having a display area and a peripheral area, a plurality of pixel units, a plurality of signal lines, and a testing circuit. The signal...
8102053 Displacement detection pattern for detecting displacement between wiring and via plug, displacement detection method, and semiconductor device  
A displacement detection pattern, usable for detection of a relative displacement between a wiring and a via plug, includes a wiring provided between via plugs and a conductor. The conductor is...
8097475 Method of production of a contact structure  
A probe card having a plurality of silicon finger contactors contacting pads provided on a tested semiconductor wafer and a probe board mounting the plurality of silicon finger contactors on its...
8084769 Testkey design pattern for gate oxide  
A testkey design pattern includes a least one conductive contact, at least one conductive line of a first width vertically and electrically connected to the conductive contact, and at least one...
8084770 Test structures for development of metal-insulator-metal (MIM) devices  
In the present electronic test structure comprising, a conductor is provided, overlying a substrate. An electronic device overlies a portion of the conductor and includes a first electrode...
8084872 Overlay mark, method of checking local aligmnent using the same and method of controlling overlay based on the same  
An overlay mark is described, including N sets of parallel x-directional linear patterns respectively defined by N (≧2) exposure steps and N sets of parallel y-directional linear patterns r...
8080823 IC chip package and image display device incorporating same  
A liquid crystal driver mounting package in accordance with an embodiment of the present invention contains a film base material and a liquid crystal driver connected to each other via an...
8076951 Spray cooling thermal management system and method for semiconductor probing, diagnostics, and failure analysis  
A micro-spray cooling system beneficial for use in testers of electrically stimulated integrated circuit chips is disclosed. The system includes micro-spray heads disposed about a probe head. The...
8072076 Bond pad structures and integrated circuit chip having the same  
Bonding pad structures and integrated circuits having the same are provided. An exemplary embodiment of a bond pad structure comprises a bond pad layer. A passivation layer partially covers the...
8067769 Wafer level package structure, and sensor device obtained from the same package structure  
A wafer level package structure with a plurality of compact sensors such as acceleration sensors and gyro sensors is provided. This package structure is composed of a semiconductor wafer with...
8067830 Dual or multiple row package  
A dual or multiple row package (300) is provided which comprises a first plurality of terminals (303, 304, 305) and a second plurality of terminals (306, 307), which first and second plurality of...
8062911 Method of manufacturing a semiconductor integrated circuit device and a method of manufacturing a thin film probe sheet for using the same  
A probe having a sufficient height is manufactured by selectively depositing, over the main surface of a wafer, a copper film in a region in which a metal film is to be formed and a region which...
8064832 Method and test system for determining gate-to-body current in a floating body FET  
In one disclosed embodiment, the present method for determining a gate-to-body current for a floating body FET comprises measuring at least three unique gate-to-body currents corresponding to at...
Matches 1 - 50 out of 1197 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >