Matches 301 - 338 out of 338 < 1 2 3 4 5 6 7
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5294823 SOI BICMOS process  
This invention is an SOI BICMOS process which uses oxygen implanted wafers as the starting substrate. The bipolar transistor is constructed in two stacked epitaxial layers on the surface of the...
5272367 Fabrication of complementary n-channel and p-channel circuits (ICs) useful in the manufacture of dynamic random access memories (drams)  
A process for fabricating n-channel and p-channel metal-oxide-semiconductor devices in the manufacture of very large scale integrated circuits, such as high density dynamic random access memories...
5256892 Semiconductor memory device wherein gate electrode thickness is greater in the memory cells than in the peripheral cells  
An attempt was made to increase the film thickness of at least a portion of word lines over which a storage node electrode of the capacitor for storing charges extends in a DRAM having word lines,...
5256894 Semiconductor device having variable impurity concentration polysilicon layer  
The present invention relates to a semiconductor device used as a gate electrode or interconnection, in which a polysilicon layer in a laminate comprising a polysilicon layer doped with an impurity...
5247198 Semiconductor integrated circuit device with multiplayered wiring  
A semiconductor integrated circuit device capable of having a high integration density and excellent performance and a method of fabricating the semiconductor integrated circuit device are...
5243213 MIS semiconductor device formed by utilizing SOI substrate having a semiconductor thin film formed on a substrate through an insulating layer  
The present invention is directed to a MIS semiconductor device having a semiconductor layer formed on an insulating substrate and a gate electrode formed on this semiconductor layer through a gate...
5221853 MOSFET with a refractory metal film, a silicide film and a nitride film formed on and in contact with a source, drain and gate region  
Selective deposition of a refractory metal on a silicon substrate utilizing high temperatures and a silane reduction process in which the flow rate ratio of silane to refractory metal halide gas is...
5214305 Polycide gate MOSFET for integrated circuits  
A method is described for fabricating a lightly doped drain MOSFET integrated circuit device which overcomes the peeling problems of refractory metal silicide layers on a polycide gate. The process...
5210435 ITLDD transistor having a variable work function  
A semiconductor device and process wherein an ITLDD device (60) is formed having an inverse-T (IT) transistor gate with a variable work function (Φ) across the gate. The variable work function is...
5192992 BICMOS device and manufacturing method thereof  
A BICMOS device and manufacturing method wherein the gates of PMOS and NMOS transistors are formed by forming a first polysilicon layer which is not implanted by an impurity and forming a second...
5190886 Semiconductor device and method of production  
A novel semiconductor device and method of production of such a device are provided. Both the N and P channels of the novel semiconductor device are formed by contact self-alignment, thereby...
5151761 Nonvolatile semiconductor memory device with isolated gate electrodes  
A nonvolatile semiconductor memory device is disclosed, which includes a semiconductor substrate, a field oxidation film selectively formed on the semiconductor substrate, a first gate insulating...
5150178 Gate structure for a semiconductor memory device  
In a semiconductor memory device of multistage gate structure, the second stage gate electrode (control gate electrode) is of superposed-layer structure of a second polysilicon layer and a high...
5060029 Step cut type insulated gate SIT having low-resistance electrode and method of manufacturing the same  
This invention provides a step cut type insulated gate static induction tsistor having a first main electrode formed in one major surface of a semiconductor substrate, a second main electrode...
5034348 Process for forming refractory metal silicide layers of different thicknesses in an integrated circuit  
A method for forming reactive metal silicide layers at two spaced locations on a silicon substrate, which layers can be of different thicknesses and/or of different reactive metals is provided. A...
5031008 MOSFET transistor  
A MOSFET transistor, in which source and drain regions are formed at a certain distance away from each other in a surface area of a semiconductor substrate having a first conductivity type, and a...
5027185 Polycide gate FET with salicide  
A process for forming a field-effect-transistor structure upon a silicon substrate includes the steps of sequentially depositing a polysilicon layer and a refractory metal silicide layer over a...
5001527 Semiconductor device with thin insulation film  
In the step of forming a thin insulation film with the thickness of less than 1,000 Å on the polycide electrode and wiring after formiung the polycide electrode and wiring, a semiconductor device...
4990998 Semiconductor device to prevent out-diffusion of impurities from one conductor layer to another  
A semiconductor device includes a first conductor layer into which is diffused an impurity for lowering the resistance, and a second conductor layer provided on the upper side of the first...
4937643 Devices having tantalum silicide structures  
A method for fabricating a device which includes a tantalum silicide structure, and which is essentially free of conductive etch residues, is disclosed. The method includes the steps of depositing...
4933994 Method for fabricating a self-aligned lightly doped drain semiconductor device with silicide  
A method for using a self-aligned metallic mask for formation of a shallow source/drain, lightly doped drain metal-oxide-semiconductor device having a self-aligned low-resistivity...
4912061 Method of forming a salicided self-aligned metal oxide semiconductor device using a disposable silicon nitride spacer  
A method of fabricating a SALICIDED self aligned metal oxide semiconductor device using a disposable silicon nitride spacer, metal silicide and a single implant step for the source, drain and gate...
4906589 Inverse-T LDDFET with self-aligned silicide  
A method of fabricating an inverse-T LDDFET with salicide on a substrate is disclosed. The initial steps include anisotropic silicon nitride and incomplete polysilicon etching steps followed by an...
4897368 Method of fabricating a polycidegate employing nitrogen/oxygen implantation  
Disclosed is a method of fabricating a polycidegate in semiconductor device which has a step of forming a conductor film of polysilicon on a substrate, a step of forming an ion implanted layer by...
4841347 MOS VLSI device having shallow junctions and method of making same  
A semiconductor device and method of making is disclosed wherein the semiconductor device includes a MOSFET with very shallow source and drain regions. The high sheet resistivity normally...
4818715 Method of fabricating a LDDFET with self-aligned silicide  
A method of fabricating a lightly-doped drain field effect transistor (LDDFET) with or without self-aligned silicide (salicide) on a substrate is disclosed. The initial steps include either (1)...
4804636 Process for making integrated circuits having titanium nitride triple interconnect  
Disclosed is a process for making VLSI integrated circuits and a local interconnect system, wherein first poly, second poly and moat are all interconnected in any desired pattern by a TiN local...
4780394 Photosensitive semiconductor device and a method of manufacturing such a device  
A photosensitive semiconductor device is provided comprising transparent gates, whose side walls are made from silicide and which, apart from these side walls, are formed from polycrystalline silicon.
4735680 Method for the self-aligned silicide formation in IC fabrication  
The invention discloses an improved process to form a silicide layer on an integrated circuit structure. The conventional lateral silicide growth is prevented by employing a slot configuration...
4635347 Method of fabricating titanium silicide gate electrodes and interconnections  
A method for constructing titanium silicide integrated circuit gate electrodes and interconnections is disclosed. The method finds particularly useful applications in metal-oxide semiconductor...
4612258 Method for thermally oxidizing polycide substrates in a dry oxygen environment and semiconductor circuit structures produced thereby  
A method of thermally oxidizing polycide substrates in a dry oxygen environment as well as a MOSFET structure provided by the method are disclosed. The method includes heating a plurality of...
4593454 Process for manufacturing an integrated circuit with tantalum silicide connections utilizing self-aligned oxidation  
The invention concerns an integrated circuit the monocrystalline or polycrystalline silicon zones of which the source, gate and drain are covered with tantalum silicide TaSi 2 while the remainder...
4566175 Method of making insulated gate field effect transistor with a lightly doped drain using oxide sidewall spacer and double implantations  
A transistor for VLSI devices employs a phosphorus implant and lateral diffusion performed after the sidewall oxide etch to thereby reduce the impurity concentration and provide a graded junction...
4554726 CMOS Integrated circuit technology utilizing dual implantation of slow and fast diffusing donor ions to form the n-well  
To minimize the number of independent masking operations in the manufacture of a CMOS integrated circuit device using twin tub technology, the n-tub is made by separate phosphorus and arsenic...
4450620 Fabrication of MOS integrated circuit devices  
In an MOS integrated circuit device, a multilayer polysilicon/metallic-silicide gate-level metallization structure is patterned to form gates and associated interconnects. Some of the interconnects...
4384301 High performance submicron metal-oxide-semiconductor field effect transistor device structure  
A novel metal-oxide-semiconductor (MOS) field effect transistor having enhanced oxide thickness at the edge of the gate electrode and having metal silicide regions in the gate electrode and source...
4128670 Fabrication method for integrated circuits with polysilicon lines having low sheet resistance  
A method and structure for polysilicon lines which include a silicide layer for providing a low sheet resistance. The invention may be employed in a polysilicon gate MOSFET process for integrated...
4102733 Two and three mask process for IGFET fabrication  
Semiconductor wafer processes employing two and three masks are disclosed for fabricating a plurality of insulated gate field effect transistors (IGFETs) to be used singly as discrete devices or...
Matches 301 - 338 out of 338 < 1 2 3 4 5 6 7