|
Match
|
Document |
Document Title |
|
|
5796130 |
Non-rectangular MOS device configurations for gate array type integrated circuits
A novel configuration for MOS devices employed in a partially generic gate array type chip having large numbers of generally MOS devices. The MOS devices have a non-rectangular configuration and...
|
|
|
5796166 |
Tasin oxygen diffusion barrier in multilayer structures
A multilayer structure having an oxygen or dopant diffusion barrier fabricated of an electrically conductive, thermally stable material of refractory metal-silicon-nitrogen which is resistant to...
|
|
|
5793083 |
Method for designing shallow junction, salicided NMOS transistors with decreased electrostatic discharge sensitivity
A technique for providing a design window for scaled technologies in which good electrostatic discharge/electrical over stress damage and optimum transistor operation can be achieved without the...
|
|
|
5789772 |
Semi-insulating surface light emitting devices
Light emitting devices are requiring greater switching speeds to achieve greater modulation bandwidths. The problems of intrinsic capacitance associated with conventional semiconductor...
|
|
|
5783850 |
Undoped polysilicon gate process for NMOS ESD protection circuits
An improved process and integrated-circuit having CMOS (NMOS and/or PMOS) devices formed on a substrate and a NMOS electro static discharge circuit formed in a P well on the substrate. The...
|
|
|
5767558 |
Structures for preventing gate oxide degradation
The degradation of integrity of the gate oxide in a CMOS transistor due to the formation of a tungsten silicide strapping layer on the polycrystalline silicon gate as a result of the migration of...
|
|
|
5760451 |
Raised source/drain with silicided contacts for semiconductor devices
A contact for a semiconductor device is provided by depositing a layer of palladium on a silicon substrate, causing the palladium to react with the substrate for forming palladium silicide,...
|
|
|
5757045 |
CMOS device structure with reduced risk of salicide bridging and reduced resistance via use of a ultra shallow, junction extension, ion implantation
A method for forming a CMOS device, with improved yield, performance and reliability characteristics, has been developed. Yield improvements have been addressed by the use of a dual insulator...
|
|
|
5751048 |
Semiconductor device having a contact window structure
A structure of a semiconductor device is disclosed whereby a gate insulating layer, a polycrystalline silicon layer, a tungsten silicide layer and a first insulating layer are formed on a...
|
|
|
5736461 |
Self-aligned cobalt silicide on MOS integrated circuits
A method of forming cobalt silicide on source/drain regions and polysilicon gate areas of an MOS integrated circuit uses an improved technique to prevent unwanted oxidation of cobalt or growth of...
|
|
|
5736767 |
Semiconductor device including a CMOSFET of a single-gate
A semiconductor device including a CMOSFET having first and second channel type MOSFETs, respectively formed in a first semiconductor region of a first conductivity type and in a second...
|
|
|
5726479 |
Semiconductor device having polysilicon electrode minimization resulting in a small resistance value
A polysilicon electrode is formed in an active area surrounded by an isolation on a silicon substrate with a gate oxide film sandwiched therebetween, a polysilicon wire is formed on the isolation,...
|
|
|
5723893 |
Method for fabricating double silicide gate electrode structures on CMOS-field effect transistors
A method is described for fabricating field effect transistors (FETs) having double silicide gate electrodes and interconnecting lines for CMOS circuits. The method reduces the IR voltage drops and...
|
|
|
5710454 |
Tungsten silicide polycide gate electrode formed through stacked amorphous silicon (SAS) multi-layer structure.
A method for forming a tungsten silicide polycide gate electrode within a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), and the tungsten silicide polycide gate electrode which is...
|
|
|
5693966 |
Power MOS transistor
Propagation delay times of an input signal from an input terminal to respective gates are equalized and accelerated with a power MOS transistor that includes a plurality of transistor blocks. The...
|
|
|
5693550 |
Method of fabricating self-aligned silicide device using CMP
A titanium film and a polysilicon film are caused to react with each other to produce a TiSi 2 layer of silicide. Thereafter, an upper end of a side wall is polished off to remove an electrically...
|
|
|
5682055 |
Method of forming planarized structures in an integrated circuit
A method is provided for forming an improved planar structure of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A field oxide is grown across the...
|
|
|
5675167 |
Enhancement-type semiconductor having reduced leakage current
A semiconductor device having an enhancement-type MOS structure which can prevent large leakage current is disclosed. A high-concentration region for threshold-value regulation use formed in a...
|
|
|
5672901 |
Structure for interconnecting different polysilicon zones on semiconductor substrates for integrated circuits
A method of forming interconnections of devices of integrated circuits, especially interconnecting spaced source/drain regions and/or gate regions, and the resulting structures are provided. An...
|
|
|
5668392 |
Low capacitance and low V.sub.t annular MOSFET design for phase lock loop applications
Low capacitance, low threshold voltage annular MOSFET transistors are disclosed. Both low junction capacitance and low threshold voltage are achieved without degradation of drain current due to...
|
|
|
5668394 |
Prevention of fluorine-induced gate oxide degradation in WSi polycide structure
A new method of fabricating a polycide gate is described. A gate polysilicon layer is provided a gate oxide layer on the surface of a substrate. A thin conducting diffusion barrier is deposited...
|
|
|
5650648 |
Integrated circuit structure having floating electrode with discontinuous phase of metal silicide formed on a surface thereof and process for making same
A process is disclosed for forming an integrated circuit device, such as an EPROM device, with a floating gate electrode with a discontinuous phase of metal silicide formed on a surface thereof is...
|
|
|
5648673 |
Semiconductor device having metal silicide film on impurity diffused layer or conductive layer
A semiconductor device and a method of fabricating such a semiconductor device in which a silicon nitride film constituting a protective film for ion implantation is used for improving the device...
|
|
|
5641983 |
Semiconductor device having a gate electrode having a low dopant concentration
In a CMOS-element-containing semiconductor device, the CMOS element comprises: a silicon substrate; an n-channel MOS element formed on the silicon substrate and including an n-type source/drain...
|
|
|
5640038 |
Integrated circuit structure with self-planarized layers
An integrated circuit structure including a conductive layer, a first dielectric layer overlying the conductive layer, a second dielectric layer overlying both the first dielectric layer and the...
|
|
|
5640035 |
MOSFET having improved driving performance
A gate oxide film is formed on the surface of a P-type silicon substrate. A gate electrode is formed on the gate oxide film. Phosphorus is ion-implanted into the P-type silicon substrate, using the...
|
|
|
5637903 |
Depleted gate transistor for high voltage operation
A process for fabricating MOSFET structures, using one gate oxide thickness, but resulting in both low and high operating voltage devices, has been developed. A fabrication sequence is described...
|
|
|
5635746 |
Semiconductor device comprising a salicide structure
After formation a gate electrode and source/drain regions, N ions or O ions are implanted into a predetermined region using a resist mask, and a Ti layer is deposited on the entire face of a...
|
|
|
5625217 |
MOS transistor having a composite gate electrode and method of fabrication
A novel, reliable, high performance MOS transistor with a composite gate electrode which is compatible with standard CMOS fabrication processes. The composite gate electrode comprises a polysilicon...
|
|
|
5621236 |
Gate-to-drain overlapped MOS transistor fabrication process and structure thereby
A method for fabricating a gate-to-drain overlapped MOS transistor in which gate-to-drain capacitance is lower and a structure thereby. A pad oxide layer is formed over a substrate having a first...
|
|
|
5621232 |
Semiconductor device including a local interconnection between an interconnection layer and an adjoining impurity region
A p-type silicon substrate is provided at its main surface with n-type impurity regions with a space between each other. A gate electrode is formed on a region between the n-type impurity regions...
|
|
|
5619057 |
Complex film overlying a substrate with defined work function
Disclosed is a method and an apparatus for making devices with low barrier height. In fabricating an n-channel and p-channel devices, hemisphere grains, silicon crystal grains and metal silicide...
|
|
|
5616948 |
Semiconductor device having electrically coupled transistors with a differential current gain
A semiconductor device includes a pass transistor (28) electrically coupled to a driver transistor (16) by a common drain region (52). The pass transistor (28) includes the pass gate electrode (44)...
|
|
|
5600168 |
Semiconductor element and method for fabricating the same
This invention relates to MOS transistors and a method for fabricating the MOS transistors having LDD (Lightly Doped Drain) structures, which comprises a first conduction type semiconductor...
|
|
|
5600177 |
Semiconductor device having an electrically conductive layer including a polycrystalline layer containing an impurity and a metallic silicide layer
The upper and lateral surfaces of a polycide electrode comprising a P + -type polycrystalline silicon layer 6 and a tungsten silicide layer 13 are covered with silicon nitride films 9, 9A....
|
|
|
5600165 |
Semiconductor device with antireflection film
A semiconductor device in which patterning is effected using a silicon oxynitride (SiON) based thin film as an anti-reflection film and in which electrical properties are prohibited from being...
|
|
|
5585659 |
Complementary metal-insulator-semiconductor devices
A method for fabricating semiconductor devices wherein polysilicon gates for complementary-type field-effect semiconductor devices are formed of polysilicon to which impurity doped simultaneously...
|
|
|
5569947 |
Insulated-gate field-effect transistor in a semiconductor device in which source/drain electrodes are defined by formation of silicide on a gate electrode and a field-effect transistor
For manufacturing an insulated-gate field-effect transistor in a semiconductor device, a refractory metal film is formed on a semiconductor substrate with an insulating film being interposed...
|
|
|
5541455 |
Method of forming low resistance contacts at the junction between regions having different conductivity types
A thin film transistor structure having a first and a second polycrystalline silicon layer of different conductivity types (P and N) has a high resistance contact at the resultant P-N junction....
|
|
|
5502324 |
Composite wiring layer
An electrode wiring layer of a semiconductor device according to this invention includes a first conductive portion formed of polycrystalline silicon or the like, and second conductive portions...
|
|
|
5498897 |
Transistor layout for semiconductor integrated circuit
A semiconductor integrated circuit comprising a MOSFET having a metal wiring layer formed via an insulating film above and along the gate electrode of the MOSFET. The MOSFET is structured such that...
|
|
|
5455444 |
Double polysilicon electrostatic discharge protection device for SRAM and DRAM memory devices
A semiconductor ESD device on a substrate is covered with SiO 2 and FOX regions, made by forming a blanket first gate layer on the device including the SiO 2 and FOX regions, patterning the first...
|
|
|
5444302 |
Semiconductor device including multi-layer conductive thin film of polycrystalline material
In forming an electrode 2 on a silicon 6 oxide film 5 on a semiconductor substrate 4 through a silicon oxide film 5, for example, the gate electrode 2 is structured in a laminated structure of a...
|
|
|
5428244 |
Semiconductor device having a silicon rich dielectric layer
The adhesion between a metallic silicide film and a dielectric layer of a semiconductor device is improved. Formed on a silicon substrate is a gate dielectric layer formed on which is a metallic...
|
|
|
5416352 |
Gate electrode formed on a region ranging from a gate insulating film to a field insulating film
The invention relates to a semiconductor device having an electrode formed on an region ranging from its thin insulating film in an element forming region to its thick insulating film in an...
|
|
|
5399896 |
FET with a T-shaped gate of a particular structure
A method for producing a T-shaped gate electrode of a semiconductor device including forming an insulating film on a semiconductor substrate, etching away a prescribed portion of the insulating...
|
|
|
5384478 |
Mask ROM process
A semiconductor device and a method of manufacturing a semiconductor device includes the steps of forming a first conductivity type layer on one surface of a work piece comprising a semiconductor...
|
|
|
5355010 |
Semiconductor device with a dual type polycide layer comprising a uniformly p-type doped silicide
A semiconductor device comprising a semiconductor substrate, an insulating film formed on the semiconductor substrate, and a polycide film including a polysilicon layer and a silicide layer formed...
|
|
|
5341014 |
Semiconductor device and a method of fabricating the same
A semiconductor device of the present invention includes a semiconductor substrate, a p-type impurity diffused region formed in the semiconductor substrate, and a polycide interconnection...
|
|
|
5331170 |
Static type random access memory device with stacked memory cell free from parasitic diode
A static type random access memory cell comprises two n-channel type driver transistors formed in a major surface portion of a p-type silicon substrate, two n-channel type transfer transistors...
|