|
Match
|
Document |
Document Title |
|
|
8171441 |
Integrated circuit devices and methods and apparatuses for designing integrated circuit devices
Methods and apparatuses to design an Integrated Circuit (IC) with a shielding of wires. In at least one embodiment, a shielding mesh of at least two reference voltages (e.g., power and ground) is...
|
|
|
8169039 |
Semiconductor device
A disclosed semiconductor device includes an MOS transistor having an N-type low-concentration drain region, a source region, an ohmic drain region, a P-type channel region, an ohmic channel...
|
|
|
8169038 |
Semiconductor device and method of manufacturing the same
A semiconductor device and a method of manufacturing the same are disclosed. The method includes forming ion impurity regions of a first conductivity type by forming a trench in a semiconductor...
|
|
|
8164139 |
MOSFET structure with guard ring
A trench Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) structure with guard ling, includes: a substrate including an epi layer region on the top thereof a plurality of source and body...
|
|
|
8166434 |
Integrated circuit devices and methods and apparatuses for designing integrated circuit devices
Methods and apparatuses to design an Integrated Circuit (IC) with a shielding of wires. In at least one embodiment, a shielding mesh of at least two reference voltages (e.g., power and ground) is...
|
|
|
8159024 |
High voltage (>100V) lateral trench power MOSFET with low specific-on-resistance
In one aspect, a lateral MOS device is provided. The lateral MOS device includes a gate electrode disposed at least partially in a gate trench to apply a voltage to a channel region, and a drain...
|
|
|
8161442 |
Integrated circuit devices and methods and apparatuses for designing integrated circuit devices
Methods and apparatuses to design an Integrated Circuit (IC) with a shielding of wires. In at least one embodiment, a shielding mesh of at least two reference voltages (e.g., power and ground) is...
|
|
|
8148788 |
Semiconductor device and method of manufacturing the same
The invention is directed to reduction of a manufacturing cost and enhancement of a breakdown voltage of a PN junction portion abutting on a guard ring. An N− type semiconductor layer is formed o...
|
|
|
8148783 |
Semiconductor device
Semiconductor device including semiconductor layer, first impurity region on surface layer portion of semiconductor layer, body region at interval from first impurity region, second impurity region...
|
|
|
8143679 |
Termination structure for power devices
A semiconductor power device includes an active region configured to conduct current when the semiconductor device is biased in a conducting state, and a termination region along a periphery of the...
|
|
|
8143680 |
Gated diode with non-planar source region
A gated-diode semiconductor device or similar component and a method of fabricating the device. The device features a gate structure disposed on a substrate over a channel and adjacent a source and...
|
|
|
8133773 |
Apparatus and method for reducing photo leakage current for TFT LCD
In one aspect of the invention, the method of forming a TFT array panel includes forming a patterned first conductive layer on a substrate, forming a gate insulating layer on the patterned first...
|
|
|
8134207 |
High breakdown voltage semiconductor circuit device
In a high breakdown voltage semiconductor element among elements integrated together on an SOI substrate in which its rated voltage is shared between an embedded oxide layer and a drain region...
|
|
|
8125052 |
Seal ring structure with improved cracking protection
An integrated circuit structure includes a semiconductor chip comprising a plurality of dielectric layers, wherein the plurality of dielectric layers includes a top dielectric layer; and a first...
|
|
|
8119460 |
Semiconductor device and method of forming the same
A semiconductor device includes a plurality of transistors disposed on a semiconductor substrate, a device isolation layer disposed around the transistors, a guard ring disposed to surround the...
|
|
|
8122412 |
Shelding mesh design for an integrated circuit device
Methods and apparatuses to design an Integrated Circuit (IC) with a shielding of wires. In at least one embodiment, a shielding mesh of at least two reference voltages (e.g., power and ground) is...
|
|
|
8115253 |
Ultra high voltage MOS transistor device
An ultra high voltage MOS transistor device includes a substrate having a first conductive type, a first well having a second conductive type and a second well having the first conductive type...
|
|
|
8110449 |
Semiconductor device and method of manufacturing the same
The HVIC includes a dielectric layer and an SOI active layer stacked on a silicon substrate, a transistor formed in the surface of the SOI active layer, and a trench isolation region formed around...
|
|
|
8110853 |
Guard ring structures for high voltage CMOS/low voltage CMOS technology using LDMOS (lateral double-diffused metal oxide semiconductor) device fabrication
A semiconductor structure. The semiconductor structure includes a semiconductor substrate, a first transistor on the semiconductor substrate, and a guard ring on the semiconductor substrate. The...
|
|
|
8097925 |
Integrated circuit guard rings
Integrated circuits with guard rings are provided. Integrated circuits may include internal circuitry that is sensitive to external noise sources. A guard ring may surround the functional circuitry...
|
|
|
8093676 |
Semiconductor component including an edge termination having a trench and method for producing
A semiconductor component includes a semiconductor body having a first side, a second side, an edge delimiting the semiconductor body in a lateral direction, an inner region and an edge region. A...
|
|
|
8093145 |
Methods for operating and fabricating a semiconductor device having a buried guard ring structure
Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation....
|
|
|
8080846 |
Semiconductor device having improved breakdown voltage and method of manufacturing the same
A semiconductor device is disclosed which improves the breakdown voltage of a planar-type junction edge terminating structure. The device includes an n-type semiconductor substrate layer common to...
|
|
|
8072035 |
Semiconductor device and method of manufacturing the same
In an LCD driver, in a high voltage resistant MISFET, end portions of a gate electrode run onto electric field relaxing insulation regions. Wires to become source wires or drain wires are formed on...
|
|
|
8074197 |
Shielding mesh design for an integrated circuit device
Methods and apparatuses to design an Integrated Circuit (IC) with a shielding of wires. In at least one embodiment, a shielding mesh of at least two reference voltages (e.g., power and ground) is...
|
|
|
8063445 |
Semiconductor device and method of manufacturing the same
Provided is a semiconductor device which includes a metal oxide semiconductor (MOS) transistor having high driving performance and high withstanding voltage with a thick gate oxide film. In the...
|
|
|
8053848 |
Semiconductor device and method of forming the same
A semiconductor device includes a plurality of transistors disposed on a semiconductor substrate, a device isolation layer disposed around the transistors, a guard ring disposed to surround the...
|
|
|
8049295 |
Coupling well structure for improving HVMOS performance
A semiconductor structure includes a substrate, a first well region of a first conductivity type overlying the substrate, a second well region of a second conductivity type opposite the first...
|
|
|
8039905 |
Semiconductor device
A semiconductor device includes a substrate having a first area and a second area, a first transistor in the first area, a second transistor in the second area, an isolation layer between the first...
|
|
|
8039906 |
High-voltage metal oxide semiconductor device and fabrication method thereof
A high-voltage metal oxide semiconductor device comprising a main body of a first conductivity type, a conductive structure, a first well of a second conductivity type, a source region of the first...
|
|
|
8030702 |
Trenched MOSFET with guard ring and channel stop
A trenched MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) with a guard ring and a channel stop, including: a substrate including an epi layer region on the top thereof; a plurality of...
|
|
|
8021984 |
Method for manufacturing semiconductor
A method for manufacturing a semiconductor includes forming an active region for an ESD device, an active region for a first polygate and the semiconductor, and a second polygate having a form of a...
|
|
|
8022480 |
Semiconductor device and method for manufacturing the same
Disclosed are a semiconductor device and a method for manufacturing the same. The semiconductor device includes at least two of first and second conductive-type high-voltage transistors and first...
|
|
|
8008734 |
Power semiconductor device
A power semiconductor device is provided having a field plate that employs a thick metal film in an edge termination structure and which permits edge termination structure width reduction even with...
|
|
|
8004051 |
Lateral trench MOSFET having a field plate
One embodiment relates to an integrated circuit that includes a lateral trench MOSFET disposed in a semiconductor body. The lateral trench MOSFET includes source and drain regions having a body...
|
|
|
8004039 |
Field effect transistor with trench-isolated drain
A MOS transistor includes a body region of a first conductivity type, a conductive gate and a first dielectric layer, a source region of a second conductivity type formed in the body region, a...
|
|
|
7999317 |
Semiconductor device and manufacturing method thereof
A p-type body region and an n-type buffer region are formed on an n− drift region. An n++ emitter region and a p++ contact region are formed on the p-type body region in contact with each other. A...
|
|
|
7999333 |
Semiconductor device
In a conventional semiconductor device, there has been a problem that, in a region where a wiring layer to which a high electric potential is applied traverses a top surface of an isolation region,...
|
|
|
7994589 |
Semiconductor device and method for fabricating the same
A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in...
|
|
|
7973361 |
High breakdown voltage semiconductor device and fabrication method of the same
A high breakdown voltage semiconductor device is formed using an SOI substrate comprising a support substrate, an insulating film, and an active layer. The high breakdown voltage semiconductor...
|
|
|
7968936 |
Quasi-vertical gated NPN-PNP ESD protection device
Fashioning a quasi-vertical gated NPN-PNP (QVGNP) electrostatic discharge (ESD) protection device is disclosed. The QVGNP ESD protection device has a well having one conductivity type formed...
|
|
|
7968976 |
Guard ring extension to prevent reliability failures
An embodiment of the present invention is a technique to prevent reliability failures in semiconductor devices. A trench is patterned in a polyimide layer over a guard ring having a top metal...
|
|
|
7964912 |
High-voltage vertical transistor with a varied width silicon pillar
In one embodiment, a vertical HVFET includes a pillar of semiconductor material a pillar of semiconductor material arranged in a loop layout having at least two substantially parallel and...
|
|
|
7964931 |
Semiconductor device
A semiconductor device 1 includes a square substrate 2, first RESURF structures 3 in the shape of planar stripes on an element area 10 of a main surface of the substrate 2, a transistor T arranged...
|
|
|
7960198 |
Method of making a semiconductor device with surge current protection
A wide bandgap semiconductor device with surge current protection and a method of making the device are described. The device comprises a low doped n-type region formed by plasma etching through...
|
|
|
7960781 |
Semiconductor device having vertical charge-compensated structure and sub-surface connecting layer and method
In one embodiment, a semiconductor device is formed having vertical localized charge-compensated trenches, trench control regions, and sub-surface doped layers. The vertical localized...
|
|
|
7952145 |
MOS transistor device in common source configuration
A semiconductor device includes a semiconductor substrate, a first p-channel laterally diffused metal oxide semiconductor (LDMOS) transistor formed over the semiconductor substrate and additional...
|
|
|
7948039 |
Semiconductor device and method for fabricating the same
A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in...
|
|
|
7936042 |
Field effect transistor containing a wide band gap semiconductor material in a drain
A field effect transistor comprising a silicon containing body is provided. After formation of a gate dielectric, gate electrode, and a first gate spacer, a drain side trench is formed and filled...
|
|
|
7927887 |
Method of fabricating a dielectric-modulated field effect transistor comprising a biomolecules layer formed in a space where a sacrificial layer has been removed
The present invention relates to a Field-Effect Transistor (FET) and, more particularly, to a Dielectric-Modulated Field-Effect Transistor (DMFET) and a method of fabricating the same. A DMFET...
|