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Match Document Document Title
7626267 Semiconductor integrated circuit device including wiring lines and interconnections  
Interconnections are formed over an interlayer insulating film which covers MISFETQ 1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a...
7622796 Semiconductor package having a bridged plate interconnection  
A semiconductor package is disclosed. The package includes a leadframe having drain, source and gate leads, and a semiconductor die coupled to the leadframe, the semiconductor die having a...
7622779 Interconnection architecture and method of assessing interconnection architecture  
A multi-celled chip. The chip includes a plurality of hexagonal cells arranged in an array. A plurality of interconnects including Y's connect the cells in clusters of three cells each, so that...
7622767 Semiconductor device with T-shaped gate electrode and hollow region adjacent the gate electrode  
In a semiconductor device, a SiN first protective insulating film is formed on a semiconductor layer. A T-shaped gate electrode is formed on the semiconductor layer. A SiN second protective...
7622758 CMOS image sensor with improved performance incorporating pixels with burst reset operation  
A reset transistor includes a floating diffusion region for detecting a charge, a junction region for draining the charge, a gate for controlling a transfer of the charge from the floating...
7622755 Primitive cell that is robust against ESD  
A primitive cell having a gate pattern that is robust against ESD is provided. The primitive cell comprises: a high finger PMOS transistor and a low finger NMOS transistor. The high finger PMOS...
7619287 Method of forming a low capacitance semiconductor device and structure therefor  
In one embodiment a transistor is formed with a gate structure having an opening in the gate structure. An insulator is formed on at least sidewalls of the opening and a conductor is formed on the...
7619269 Semiconductor device, manufacturing process thereof and imaging device  
A semiconductor device including a pixel region in which one or more pixels are formed and a DRAM cell region in which one or more DRAM cells for storing output signals from the pixels are formed,...
7615827 Dual gate dielectric thickness devices and circuits using dual gate dielectric thickness devices  
Dual thickness devices and circuits using dual gate thickness devices. The devices include: one or more FETs of a first polarity and one or more FETs of a second and opposite polarity, the one or...
7612420 Method for doping a fin-based semiconductor device  
A method for doping a fin-based semiconductor device is disclosed. In one aspect, the method comprises patterning at least one fin, each fin comprising a top surface and a left sidewall surface and...
7612419 Wafer, semiconductor chip, and semiconductor device  
Scribe lines demarcating semiconductor chips comprise, in both the vertical direction and the horizontal direction, first-type scribe lines of the minimum width enabling cutting by dicing or other...
7612418 Monolithic power semiconductor structures including pairs of integrated devices  
Monolithic semiconductor structures having at least two pairs of two lateral semiconductor devices combined on a first surface of a single semiconductor substrate. Embodiments include connected...
7612411 Dual-gate device and method  
A memory circuit having dual-gate memory cells and a method for fabricating such a memory circuit are disclosed. The dual-gate memory cells each include a memory device and an access device sharing...
7612405 Fabrication of FinFETs with multiple fin heights  
A semiconductor structure includes a first semiconductor strip extending from a top surface of the semiconductor substrate into the semiconductor substrate, wherein the first semiconductor strip...
7608891 Thin film transistor, circuit apparatus and liquid crystal display  
A thin film transistor includes a one conductive type semiconductor layer ( 11 ); a source region ( 12 ) and a drain region ( 13 ) which are separately provided in the semiconductor layer; and a...
7605449 Enhanced segmented channel MOS transistor with high-permittivity dielectric isolation material  
By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor...
7605446 Bipolar high voltage/power semiconductor device having first and second insulated gated and method of operation  
A bipolar high voltage/power semiconductor device has a drift region having adjacent its ends regions of different conductivity types respectively. High and low voltage terminals are provided. A...
7605435 Bi-directional MOSFET power switch with single metal layer  
A bi-directional power switch is formed as a monolithic semiconductor device. The power switch has two MOSFETs formed with separate source contacts to the external package and a common drain. The...
7605409 Semiconductor device, method of manufacturing the same, sense amplifier and method of forming the same  
A semiconductor device includes first and second unit circuits. Each first unit circuit has first transistors connected in series, wherein each of the first transistors includes a first gate...
7605032 Method for producing a trench transistor and trench transistor  
In a method for producing a trench transistor, a substrate of a first conduction type is provided and a trench in the substrate and a gate dielectric in the trench are formed. A first conductive...
7602029 Configuration and method of manufacturing the one-time programmable (OTP) memory cells  
This invention discloses an one time programmable (OTP) memory. The OTP memory includes a first and a second metal oxide semiconductor (MOS) transistors connected in parallel and controlled by a...
7602028 NAND flash memory devices having 3-dimensionally arranged memory cells and methods of fabricating the same  
A NAND flash memory device includes a lower semiconductor layer and an upper semiconductor layer located over the lower semiconductor layer, a first drain region and a first source region located...
7602021 Method and structure for strained FinFET devices  
A method (and structure) of forming an electronic device includes forming at least one localized stressor region within the device.
7602019 Drive circuit and drain extended transistor for use therein  
A transistor comprises a source region of a first conductivity type and electrically communicating with a first semiconductor region. The transistor also comprises a drain region of the first...
7602013 Semiconductor device with recessed channel  
A semiconductor device includes: a layer provided on or above a semiconductor substrate, having an opening, and containing Si and Ge; and a gate provided at a position corresponding to the opening....
7598541 Semiconductor device comprising transistor pair isolated by trench isolation  
A semiconductor device has transistors (P 1 ,P 10 ,P 11 ) formed in an active region ( 22 ) isolated by a trench isolation region, and a predetermined circuit including a first and second...
7595537 MOS type semiconductor device having electrostatic discharge protection arrangement  
In a semiconductor device, a well region is formed in a semiconductor substrate, a transistor-formation region is defined in the well region. An electrostatic discharge protection device is...
7592675 Partial FinFET memory cell  
A semiconductor structure includes a semiconductor substrate, a planar PMOS device at a surface of the semiconductor substrate, and an NMOS device at the surface of the semiconductor substrate,...
7589387 SONOS type two-bit FinFET flash memory cell  
A 2-bit FinFET flash memory cell capable of storing 2 bits and a method of forming the same are provided. The memory cell includes a semiconductor fin on a top surface of a substrate, a gate...
7589369 Semiconductor constructions  
The invention includes a method in which a semiconductor substrate is provided to have a memory array region, and a peripheral region outward of the memory array region. Paired transistors are...
7589361 Standard cells, LSI with the standard cells and layout design method for the standard cells  
In automatic placing and routing, a standard cell 101 is composed of a P-channel transistor region 102 and an N-channel transistor region 103 . The P-channel transistor region 102 has a...
7586151 Insulated gate semiconductor device  
The present invention provides an insulated gate semiconductor device which has floating regions around the bottoms of trenches and which is capable of reliably achieving a high withstand voltage....
7586132 Power FET with low on-resistance using merged metal layers  
In one embodiment, relatively thin but wide metal bus strips overlying a high power FET are formed to conduct current to the source and drain narrow metal strips. A passivation layer is formed over...
7586130 Vertical field effect transistor using linear structure as a channel region and method for fabricating the same  
A vertical field effect transistor includes: an active region with a bundle of linear structures functioning as a channel region; a lower electrode, functioning as one of source and drain regions;...
7582934 Isolation spacer for thin SOI devices  
A semiconductor device comprises a semiconductor mesa overlying a dielectric layer, a gate stack formed overlying the semiconductor mesa, and an isolation spacer formed surrounding the...
7582927 Flash EEPROM cell and method of fabricating the same  
A semiconductor device including a memory cell having a memory transistor and select gate transistor and a peripheral transistor is disclosed. The memory transistor has a stacked gate structure...
7576410 Power transistor  
A power transistor has a source region, a drain region, a semiconductor body arranged between the source region and the drain region, and a plurality of nanotubes. The plurality of nanotubes are...
7575975 Method for forming a planar and vertical semiconductor structure having a strained semiconductor layer  
Forming a semiconductor structure includes providing a substrate having a strained semiconductor layer overlying an insulating layer, providing a first device region for forming a first plurality...
7573109 Semiconductor device  
A semiconductor device having high withstand strength against destruction. The semiconductor device 1 includes guard buried regions 44 b of second conductivity type concentrically provided on a...
7573108 Non-planar transistor and techniques for fabricating the same  
A non-planar transistor and methods for fabricating the same. In certain embodiments, the transistor includes an active gate and a passive gate. The active gate may be switchably coupled to a first...
7573107 Power module  
A power module that includes a power circuit assembly in which power components are electrically and mechanically connected without wires.
7573101 Embedded substrate interconnect for underside contact to source and drain regions  
A semiconductor topography ( 10 ) is provided which includes a semiconductor-on-insulator (SOI) substrate having a conductive line ( 16 ) arranged within an insulating layer ( 22 ) of the SOI...
7573099 Semiconductor device layout and channeling implant process  
A device structure and method for forming graded junction using a implant process. Embodiments of the invention comprise implanting ions into said silicon substrate to form doped regions adjacent...
7571415 Layout of power device  
A layout of a power device is provided. The layout includes a substrate, a unit array, a plurality of first, second, third and fourth signal paths, and a first, second, third and fourth port. The...
7569900 Silicon carbide high breakdown voltage semiconductor device  
A semiconductor device includes an SiC substrate, an SiC layer of a first conductivity type disposed on the upper surface of the SiC substrate, a first SiC region of a second conductivity type...
7569897 Low-capacitance contact for long gate-length devices with small contacted pitch  
Disclosed are planar and non-planar field effect transistor (FET) structures and methods of forming the structures. The structures comprise segmented active devices (e.g., multiple semiconductor...
7569883 Switching-controlled power MOS electronic device  
Power electronic MOS device of the type comprising a plurality of elementary power MOS transistors and a gate structure comprising a plurality of conductive strips realized with a first conductive...
7569876 DRAM arrays, vertical transistor structures, and methods of forming transistor structures and DRAM arrays  
The invention includes a method of forming a semiconductor construction. Dopant is implanted into the upper surface of a monocrystalline silicon substrate. The substrate is etched to form a...
7569875 Semiconductor device and a method for producing the same  
A semiconductor device having a substrate; an emitter electrode or source electrode formed on the top surface side of the substrate; a gate electrode formed on the top surface side of the...
7564105 Quasi-plannar and FinFET-like transistors on bulk silicon  
The types of quasi-planar CMOS and FinFET-like transistor devices on a bulk silicon substrate are disclosed. A first device has a doped and recessed channel formed in a shallow trench sidewall. A...
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