Matches 101 - 150 out of 188 < 1 2 3 4 >
Match Document Document Title
6329271 Self-aligned channel implantation  
A short channel insulated gate field effect transistor has within the semiconductor body that houses the transistor a buried layer of the same conductivity type as the body but of higher impurity...
6323540 Semiconductor processing method of forming a contact opening to a region adjacent a field isolation mass, and a semiconductor structure  
A semiconductor processing method of forming a contact opening to a region adjacent a field isolation mass includes, a) forming a field isolation mass within a semiconductor substrate by a trench...
6288942 Nonvolatile semiconductor storage device and its manufacturing method  
High-concentrated impurity regions 24 for isolation of bit line contacts, having the same conduction type as that of a semiconductor substrate 10, are formed in the semiconductor substrate 10 under...
6285073 Contact structure and method of formation  
The horizontal surface area required to contact semiconductor devices, in integrated circuits fabricated with trench isolation, is minimized without degrading contact resistance by utilizing the...
6278161 Transistor  
A MOSFET is fabricated by forming a trench in a semiconductor substrate, forming an insulating film in the trench, forming a gate electrode to fill in the trench, forming a gate oxide on the gate...
6271571 Uprom memory cells for non-volatile memory devices integrated on semiconductors  
A redundancy UPROM cell includes at least one memory element of EPROM or Flash type, having a control terminal and a conduction terminal to be biased, an inverter register connected to the memory...
6265743 Trench type element isolation structure  
There is provided a trench type element isolation structure wherein no recess develops in the edge part of an imbedded oxide film of a trench type element isolation. Thermal oxidation films having...
6262453 Double gate-oxide for reducing gate-drain capacitance in trenched DMOS with high-dopant concentration buried-region under trenched gate  
This invention discloses a DMOS power device supported on a substrate. The DOS power device includes a drain of a first conductivity type disposed at a bottom surface of the substrate. The DMOS...
6252274 Process for making crosspoint memory devices with cells having a source channel which is autoaligned to the bit line and to the field oxide  
A process of manufacturing cross-point matrix memory devices which have floating gate memory cells having the source channel self-aligned to the bit line and the field oxide is disclosed. The...
6232646 Shallow trench isolation filled with thermal oxide  
A semiconductor apparatus and method for producing shallow trench isolation. The method includes the steps providing a semiconductor substrate member fabricated having a thin barrier oxide layer on...
6194766 Integrated circuit having low voltage and high voltage devices on a common semiconductor substrate  
High voltage and low voltage devices are provided on a common semiconductor substrate. An integrated semiconductor circuit includes a semiconductor substrate of a first conductivity type. Well...
6188110 Integration of isolation with epitaxial growth regions for enhanced device formation  
A method of forming integrated isolation regions and active regions includes first forming a plurality of dielectric layers upon a semiconductor substrate. Then, a patterned mask is applied to...
6160297 Semiconductor memory device having a first source line arranged between a memory cell string and bit lines in the direction crossing the bit lines and a second source line arranged in parallel to the bit lines  
A semiconductor device comprises select gates and control gates of a plurality of memory cells therebetween so that gate members on upper portions of stacked gates may cross element regions. A...
6156596 Method for fabricating a complementary metal oxide semiconductor image sensor  
A method for fabricating a CMOS image sensor resolves the abnormally elevated output at the first pixel without degrading the integration of the device. The method of the invention lengthens the...
6153907 IC layout structure for MOSFET having narrow and short channel  
A specific IC layout structure for the MOSFET having a narrow and short channel, especially when the width and the length of the channel are both as small as 1 micron or less, is disclosed. In the...
6153918 Semiconductor device with improved planarity and reduced parasitic capacitance  
In a semiconductor device and a method of manufacturing the same, a dummy region which can suppress occurrence of a parasitic capacity can be provided for reducing a difference in level without...
6140691 Trench isolation structure having a low K dielectric material isolated from a silicon-based substrate  
A trench isolation structure is provided which includes a dielectric material having a relatively low dielectric constant, K, that is approximately less than 3.8. The capacitance between active...
6137148 NMOS transistor  
The NMOS transistor is provided with a semiconducting substrate (12) which is p-doped and comprises a top side (14), and with a first region (16) which is n-doped and placed into the substrate by...
6124199 Method for simultaneously forming a storage-capacitor electrode and interconnect  
A DRAM memory cell array includes a wiring layer formed at a storage-capacitor level of the cell for establishing a flipped connection of complementary bit lines, or for connecting support circuits...
6114716 Heterolithic microwave integrated circuits  
Silicon conductive vias and pedestals are disclosed for use in microwave integrated circuits. The pedestals are isolated from a ground plane on the bottom surface by glass, while the vias are used...
6111293 Silicon-on-insulator MOS structure  
A silicon-on-insulator metallic oxide semiconductor structure having a double implanted source region. By etching a trench contact window in the double implanted source region and then depositing a...
6091106 Low voltage transistor structure having a grooved gate  
Disclosed is a transistor structure having a semiconductor substrate with a active region and a field region, a recess region being defined by either the field region or the active region, a gate...
6078085 Semiconductor integrated circuit and layout apparatus in which guard-ring is interposed between input-output circuits  
A semiconductor integrated circuit is made up of a plurality of input-output circuit portions which are aligned at irregular intervals between a core portion and an external portion, a first...
6077735 Method of manufacturing semiconductor device  
A method of making semiconductor devices which enables control of the impurity concentration and fine patterning by making removal of residual stress due LOCOS oxidation compatible with the...
6069390 Semiconductor integrated circuits with mesas  
A semiconductor apparatus and method for making the same is disclosed herein in which the semiconductor apparatus includes a first active device formed in a mesa region of semiconductor material...
6064105 Data retention of EEPROM cell with shallow trench isolation using thicker liner oxide  
A shallow trench isolation structure and a method for forming the same for use with non-volatile memory devices is provided so as to maintain sufficient data retention thereof. An epitaxial layer...
6057580 Semiconductor memory device having shallow trench isolation structure  
In a nonvolatile semiconductor memory device, those sides of the gate insulating film and the floating gate electrode which oppose an inner side of a trench are oxidized to form an oxide film. The...
6046483 Planar isolation structure in an integrated circuit  
A method is provided for forming an isolation structure at a semiconducting surface of a body, and the isolation structure formed thereby. A masking layer is formed over selected regions of the...
6040597 Isolation boundaries in flash memory cores  
A wet etching process for establishing isolation grooves in a flash memory core wafer includes depositing nitride and/or oxide layers on a silicon substrate of the wafer, depositing a photoresist...
6034396 Ultra-short channel recessed gate MOSFET with a buried contact  
The transistor structure in the present invention has a recessed region on the top surface of the semiconductor substrate. The transistor has a gate insulator within the recessed region and the...
6018185 Semiconductor device with element isolation film  
The semiconductor device comprises a semiconductor substrate having an element region, an element isolation film formed on the semiconductor substrate so as to surround the element region, a gate...
5994756 Substrate having shallow trench isolation  
A semiconductor substrate having a shallow trench isolation (STI) structure and a method of manufacturing the same are provided, i.e., an isolation substrate in which grooves are selectively formed...
5990536 Integrated circuit arrangement having at least two mutually insulated components, and method for its production  
An integrated circuit arrangement having at least two components has in a substrate, an insulation structure (4', 5) between the components which covers at least one side of a trench (3) and is...
5981994 Method and semiconductor circuit for maintaining integrity of field threshold voltage requirements  
A method for maintaining a high field threshold voltage in a plurality of transistors of reduced size in a periphery region of a Flash EPROM semiconductor circuit includes forming a first...
5969393 Semiconductor device and method of manufacture of the same  
A semiconductor device comprises a semiconductor substrate having a major surface, a semiconductor region defined between at least two trenches formed in the major surface, a first insulating layer...
5949126 Trench isolation structure employing protective sidewall spacers upon exposed surfaces of the isolation trench  
A shallow trench isolation structure and method for making the same are presented. In an embodiment, a trench dielectric is formed within a shallow trench that is disposed in a semiconductor...
5949116 MOS device having a source/drain region conforming to a conductive material filled French structure in a substrate  
A MOS device and method of fabricating the same, wherein the source/drain region has polysilicon trench structure which are formed by self-alignment using silicon oxide layers as masks. The...
5949115 Semiconductor device including nickel formed on a crystalline silicon substrate  
In a MOS semiconductor device utilizing a crystalline silicon substrate, the formation of a parasitic channel is suppressed. A solution of nickel acetate is applied to a silicon substrate 101 to...
5939758 Semiconductor device with gate electrodes having conductive films  
First and second gate electrodes are formed spaced from each other on a semiconductor substrate. A pair of impurity diffusion layers are provided on both sides of the first gate electrode at the...
5936283 MOSFET for input/output protective circuit having a multi-layered contact structure with multiple contact holes on a single diffusion layer  
According to the present invention, a MOSFET for an input/output protective circuit in which a source diffusion layer, a drain diffusion layer and a gate electrode are formed on a semiconductor...
5932920 Nonvolatile memory device and manufacturing method thereof  
A nonvolatile memory device and a manufacturing method thereof are provided. The nonvolatile memory device includes memory cells which are formed in a cell array region, peripheral circuit devices...
5905285 Ultra short trench transistors and process for making same  
A field effect transistor comprising a semiconductor substrate having a transistor trench extending downward from an upper surface of the semiconductor substrate. The trench extends to a trench...
5814848 Semiconductor integrated circuit having reduced wiring capacitance  
In a semiconductor integrated circuit, the wiring capacitance of the bus line region is reduced, so that the operation speed can be increased, the power consumption can be decreased, and the chip...
5811865 Dielectric in an integrated circuit  
A method is provided for forming an improved device dielectric of a semiconductor integrated circuit, and an integrated circuit formed according to the same. For scaling geometries for use in the...
5804862 Semiconductor device having contact hole open to impurity region coplanar with buried isolating region  
A MIS type field effect transistor has a source/drain region overlain by a titanium silicide layer contiguous to an upper silicon nitride layer of a buried isolating structure embedded into a...
5786617 High voltage charge pump using low voltage type transistors  
An integrated circuit includes an N isolation buried layer underlying high density and low voltage type P channel and N channel transistors to define islands of arbitrary voltage on the substrate....
5763937 Device reliability of MOS devices using silicon rich plasma oxide films  
The invention relates to MOS devices and methods for fabricating MOS devices having multilayer metallization. In accordance with preferred embodiments, internal passivation is used for suppressing...
5742095 Method of fabricating planar regions in an integrated circuit  
A method is provided for forming a planar surface of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A gate oxide layer is formed over a silicon...
5742091 Semiconductor device having a passive device formed over one or more deep trenches  
A semiconductor device includes at least one passive device and is configured such that parasitic capacitances associated with the passive device are minimized. A substrate layer of the...
5729043 Shallow trench isolation with self aligned PSG layer  
A method for forming trench isolation and in specific shallow trench isolation(STI) using SiO 2 plugs is proposed. The SiO 2 plugs of the STI have a buried phosphorus (P) rich layer introduced...
Matches 101 - 150 out of 188 < 1 2 3 4 >