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7626235 NAND nonvolatile semiconductor memory device and method of manufacturing NAND nonvolatile semiconductor memory device  
A NAND nonvolatile semiconductor memory device that has a memory cell array region and a selection gate region, has a semiconductor layer; a gate insulating film disposed on said semiconductor...
7626227 Semiconductor device with reduced transistor breakdown voltage for preventing substrate junction currents  
A semiconductor device is provided which includes a gate electrode ( 30 ) provided on a semiconductor substrate ( 10 ), an oxide/nitride/oxide (ONO) film ( 18 ) that is formed between the gate...
7619287 Method of forming a low capacitance semiconductor device and structure therefor  
In one embodiment a transistor is formed with a gate structure having an opening in the gate structure. An insulator is formed on at least sidewalls of the opening and a conductor is formed on the...
7619286 Liquid crystal display device and method of fabricating the same  
A poly-silicon liquid crystal display device with an improved aperture ratio and a simplified method of fabricating the same are disclosed. A liquid crystal display device according to the present...
7612438 Active matrix substrate with height control member  
An active matrix substrate comprises a substrate, a plurality of adhesion parts provided on the substrate so as to have substantially the same height, and a plurality of active elements provided on...
7605434 Semiconductor memory device to which test data is written  
A semiconductor memory device of this invention includes a first bank, a second bank, and a bank decoder that selects a bank to be activated from the first and second banks. When testing operations...
7605430 Nonvolatile memory devices having a fin shaped active region and methods of fabricating the same  
A nonvolatile memory device includes a semiconductor substrate and a device isolation layer on the semiconductor substrate. A fin-shaped active region is formed between portions of the device...
7602028 NAND flash memory devices having 3-dimensionally arranged memory cells and methods of fabricating the same  
A NAND flash memory device includes a lower semiconductor layer and an upper semiconductor layer located over the lower semiconductor layer, a first drain region and a first source region located...
7602010 Multi-bit multi-level non-volatile memory device and methods of operating and fabricating the same  
In a non-volatile memory device allowing multi-bit and/or multi-level operations, and methods of operating and fabricating the same, the non-volatile memory device comprises, in one embodiment: a...
7598541 Semiconductor device comprising transistor pair isolated by trench isolation  
A semiconductor device has transistors (P 1 ,P 10 ,P 11 ) formed in an active region ( 22 ) isolated by a trench isolation region, and a predetermined circuit including a first and second...
7592661 CMOS embedded high voltage transistor  
A circuit having a high voltage, drain-extended (DE) metal-oxide-semiconductor (MOS) transistor and method for fabricating the same are provided. Generally, the circuit includes an n-channel (NMOS)...
7589368 Three-dimensional memory devices  
Memory devices are disclosed. One example of a memory device may include two layers of memory arrays each containing at least four memory cells. In particular, the memory device includes two word...
7588987 Semiconductor device and method for fabricating the same  
A semiconductor device and a method for fabricating the same selectively forms a nitride layer having high tensile stress in an NMOS transistor area, to thereby form a strained-silicon structure in...
7569889 Memory integrated circuit, in particular an SRAM memory integrated circuit, and corresponding fabrication process  
A RAM memory integrated circuit, in particular a SRAM memory integrated circuit, includes a matrix of memory cells that are arranged between two bit lines via two access transistors. The bit lines...
7563699 Semiconductor devices having line type active regions and methods of fabricating the same  
In a semiconductor device having line type active regions and a method of fabricating the semiconductor device, the semiconductor device includes a device isolation layer which defines the line...
7554151 Low voltage non-volatile memory cell with electrically transparent control gate  
An EEPROM having a charge storage element, i.e., a floating gate, in the substrate adjacent to vertically separated source and drain electrodes. An electrically transparent poly control gate allows...
7553728 Method of fabricating a non-volatile semiconductor memory  
An non-volatile semiconductor memory having a linear arrangement of a plurality of memory cell transistors, includes: a first semiconductor layer having a first conductivity type; a second...
7547936 Semiconductor memory devices including offset active regions  
A semiconductor memory device may include a substrate having a plurality of active regions and a field isolation layer on the substrate surrounding the active regions of the substrate. Each of the...
7547935 Semiconductor devices including buried digit lines that are laterally offset from corresponding active-device regions  
A method of electrically linking contacts of a semiconductor device to their corresponding digit lines. The method includes disposing a quantity of mask material into a trench through which the...
7545019 Integrated circuit including logic portion and memory portion  
An integrated circuit includes a logic portion including M conductive layers, a memory portion including N conductive layers, and at least one common top conductive layer over the logic portion and...
7541654 Semiconductor memory device and semiconductor device including multilayer gate electrode  
In a memory cell array are arranged a plurality of cell units having memory cells and selection gate transistors to select the memory cell. A first selection gate line includes a control gate of...
7541653 Mask ROM devices of semiconductor devices and method of forming the same  
Disclosed are a mask ROM device and a method of forming the same. This device includes a plurality of cells. At least one among the plurality of cells is programmed. The programmed cell includes a...
7541649 Semiconductor device having SOI substrate  
A semiconductor device includes first semiconductor layers with a first conductivity, second to fifth semiconductor layers with a second conductivity, gate electrodes, and a first wiring layer. The...
7538368 Standard cell, standard cell library, and semiconductor integrated circuit with suppressed variation in characteristics  
In a standard cell, at least one of transistors on either side of a transistor having gate length different from that of the other transistors are set to be always in the OFF state. This prevents...
7531867 Method for forming an integrated memory device and memory device  
The invention in one of the embodiments refers to a method for forming an integrated memory device, the method including a forming a plurality of bitlines, wherein forming the plurality of bitlines...
7528452 Semiconductor memory  
Borderless contacts for word lines or via contacts for bit lines are formed using interconnect patterns, a part of which is removed. A semiconductor memory includes: a plurality of active regions...
7525137 TFT mask ROM and method for making same  
There is provided a monolithic three dimensional TFT mask ROM array. The array includes a plurality of device levels. Each of the plurality of device levels contains a first set of enabled TFTs and...
7521764 One-time programmable memory device  
A one-time programmable, dual-bit memory device comprises one MOS storage transistor having a semiconductor substrate, first and second active regions formed under the surface of the substrate...
7511340 Semiconductor devices having gate structures and contact pads that are lower than the gate structures  
Semiconductor devices have gate structures on a semiconductor substrate with first spacers on sidewalls of the respective gate structures. First contact pads are positioned between the gate...
7504688 Semiconductor device with integrated flash memory and peripheral circuit and its manufacture method  
A non-volatile semiconductor memory device includes: a non-volatile memory area including gate electrodes, each including stack of a floating gate, an inter-electrode insulating film and a control...
7495296 Semiconductor integrated circuit device  
The present invention relates to a layout of a multi-channel semiconductor integrated circuit and provides a layout of a semiconductor integrated circuit having ternary circuits in order to...
7495294 Flash devices with shared word lines  
Word lines of a NAND flash memory array are formed by concentric, rectangular shaped, closed loops that have a width of approximately half the minimum feature size of the patterning process used....
7489027 Accessible electronic storage apparatus  
A storage apparatus 10 is disclosed, that comprises a wiring substrate 11 having a first surface and a second surface, a flat type external connection terminal 12 a disposed on the first...
7489010 Semiconductor memory device  
In a semiconductor memory device with NAND cell units arranged, two first select gate lines in adjacent blocks sandwiching a bit line contact are formed to have first connection portions disposed...
7485935 Semiconductor memory device  
A semiconductor memory device is provided with plural memory cells, plural bit lines BL, each bit line being commonly connected to the plural memory cells that are arranged in the same row, plural...
7482630 NAND memory arrays  
A NAND memory array has a substrate, a source select gate formed on the substrate, and a drain select gate formed on the substrate. A string of floating-gate memory cells is formed on the substrate...
7476945 Memory having reduced memory cell size  
A memory capable of reducing the memory cell size is provided. This memory includes a first conductive type first impurity region formed on a memory cell array region of the main surface of a...
7476943 Semiconductor device having diffusion layers as bit lines and method for manufacturing the same  
A semiconductor device includes: a semiconductor region; a plurality of bit line diffusion layers formed in an upper portion of the semiconductor region and each extending in a row direction; a...
7453125 Double mesh finfet  
A multiple gate field-effect transistor is built from an overlapping mesh assembly. The assembly comprises a first layer comprising a semiconductor material formed into at least one fin, at least...
7442997 Three-dimensional memory cells  
The present invention discloses a three-dimensional memory (3D-M) with polarized 3D-ROM (three-dimensional read-only memory) cells. Polarized 3D-ROM can ensure a larger unit array and therefore, a...
7439594 Stacked non-volatile memory with silicon carbide-based amorphous silicon thin film transistors  
A stacked non-volatile memory device uses amorphous silicon based thin film transistors stacked vertically. Each layer of transistors or cells is formed from a deposited a-Si channel region layer...
7436078 Line layout structure of semiconductor memory device  
An apparatus including a trolling motor having at least one operational subsystem and the trolling motor also having an integral electronic controller for controlling the operational subsystem...
7436032 Semiconductor integrated circuit comprising read only memory, semiconductor device comprising the semiconductor integrated circuit, and manufacturing method of the semiconductor integrated circuit  
A chip with increased impact resistance, attractive design and reduced cost, and a manufacturing method thereof are provided. A semiconductor integrated circuit is formed on a large glass...
7432561 Non-volatile semiconductor memory and method for manufacturing a non-volatile semiconductor memory  
An non-volatile semiconductor memory having a linear arrangement of a plurality of memory cell transistors, includes: a first semiconductor layer having a first conductivity type; a second...
RE40532 Non-volatile memory cell and fabrication method  
Memory cell transistors with back-channel isolation are produced without using an SOI substrate. With the word line stack acting as a mask, the semiconductor material is etched on both sides of the...
7420248 Programmable random logic arrays using PN isolation  
Disclosed are a programmable, random logic device array, and a method of forming such a device. The device comprises a substrate, and a semiconductor layer above the substrate. That semiconductor...
7417283 CMOS device with dual polycide gates and method of manufacturing the same  
A CMOS device having dual polycide gates is formed by first providing a silicon substrate, which is divided into a cell area and a peripheral circuit area and has a device isolation layer, a...
7411255 Dopant barrier for doped glass in memory devices  
A semiconductor device has a diffusion barrier formed between a doped glass layer and surface structures formed on a substrate. The diffusion barrier includes alumina and optionally a nitride, and...
7408230 EEPROM device having first and second doped regions that increase an effective channel length  
Provided is an EEPROM device and a method of manufacturing the same. The EEPROM device is composed of one cell including a memory transistor and a selection transistor located in series on a...
7405470 Adaptable electronic storage apparatus  
A storage apparatus 10 is disclosed, that comprises a wiring substrate 11 having a first surface and a second surface, a flat type external connection terminal 12 a disposed on the first...
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