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7605414 MOS transistors having low-resistance salicide gates and a self-aligned contact between them  
A method for forming a self-aligned contact between two MOS transistors is described. The method supports the use of low-resistivity suicides for the formation of contacts in nanometer applications...
7569896 Transistors with stressed channels  
A MOS device having optimized stress in the channel region and a method for forming the same are provided. The MOS device includes a gate over a substrate, a gate spacer on a sidewall of the gate...
7569891 Semiconductor device with reduced contact resistance and method for manufacturing the same  
It is made possible to reduce the contact resistance of the source and drain in an n-type MISFET. A semiconductor device includes: a source and drain regions provided in a p-type semiconductor...
7564104 Low ohmic layout technique for MOS transistors  
A transistor driver circuit with a plurality of transistors, each having source and drain regions formed in a substrate. At least first and second interconnect layers are formed on top of the...
7564061 Field effect transistor and production method thereof  
A field effect transistor having a gate, a source, and a drain formed from metallic materials is disclosed that is able to supply a high driving current. In the field effect transistor, a source...
7560783 Metal-semiconductor contact, semiconductor component, integrated circuit arrangement and method  
The present invention relates to a metal-semiconductor contact comprising a semiconductor layer and comprising a metallization applied to the semiconductor layer, a high dopant concentration being...
7560758 MOSFETs comprising source/drain recesses with slanted sidewall surfaces, and methods for fabricating the same  
The present invention relates to improved metal-oxide-semiconductor field effect transistor (MOSFET) devices with stress-inducing structures located at the source and drain (S/D) regions....
7556954 MOS transistor and manufacturing method thereof  
Disclosed are a MOS transistor having a low resistance ohmic contact characteristic and a manufacturing method thereof capable of improving a drive current of the MOS transistor. A gate oxide...
7550807 Semiconductor memory  
In the non-volatile semiconductor memory in which an N-type source diffusion layer and an N-type drain diffusion layer are formed on a P-type well formed on a substrate: the source diffusion layer...
7545006 CMOS devices with graded silicide regions  
A semiconductor device includes a semiconductor substrate, a gate stack overlying the semiconductor substrate, a spacer on a sidewall of the gate stack, a lightly doped source/drain (LDD) region...
7541653 Mask ROM devices of semiconductor devices and method of forming the same  
Disclosed are a mask ROM device and a method of forming the same. This device includes a plurality of cells. At least one among the plurality of cells is programmed. The programmed cell includes a...
7538398 System and method for forming a semiconductor device source/drain contact  
The present invention discloses a semiconductor source/drain contact structure, which comprises a substrate, a source/drain region disposed in the substrate, at least one non-silicided conductive...
7525160 Multigate device with recessed strain regions  
Embodiments of the invention provide a device with a multiple gates. Stress material within recesses of a device body metal gate may cause a stress in channel regions of the device, thereby...
7514756 Semiconductor device with MISFET  
A semiconductor device includes a substrate, a semiconductor region provided in the substrate, a group of transistors including a plurality of MIS transistors and provided in the semiconductor...
7514714 Thin film power MOS transistor, apparatus, and method  
A thin film power transistor includes a plurality of first doped regions over a substrate and a second doped region forming a body. At least a portion of the body is disposed between the plurality...
7511350 Nickel alloy silicide including indium and a method of manufacture therefor  
The invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other...
7511349 Contact or via hole structure with enlarged bottom critical dimension  
An integrated circuit chip includes a buffer layer, an underlying layer, a dielectric layer, a hole, and barrier layer. The buffer layer is over the underlying layer. The dielectric layer is over...
7511348 MOS transistors with selectively strained channels  
The channels of first and second CMOS transistors can be selectively stressed. A gate structure of the first transistor includes a stressor that produces stress in the channel of the first...
7508053 Semiconductor MOS transistor device and method for making the same  
A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A gate dielectric layer is formed on an active area of a substrate. A gate electrode is patterned on the...
7501673 Semiconductor device multilayer structure, fabrication method for the same, semiconductor device having the same, and semiconductor device fabrication method  
In one embodiment, a semiconductor device includes a semiconductor substrate and a doped conductive layer formed over the semiconductor substrate. A diffusion barrier layer is formed over the doped...
7498641 Partial replacement silicide gate  
A method of forming fully silicide gates having uniform gate silicide thickness is presented. A gate dielectric is formed over a substrate. A silicon-containing layer is formed over the gate...
7498640 Self-aligned silicide process for silicon sidewall source and drain contacts and structure formed thereby  
A method (and structure formed thereby) of forming a metal silicide contact on a non-planar silicon containing region having controlled consumption of the silicon containing region, includes...
7498626 Semiconductor device and method of manufacturing the same  
The present invention provides a semiconductor device comprising a capacitive element with a very uniform capacitive value as well as a method of manufacturing the semiconductor device. In a...
7495292 Integrated circuit devices having pad contact plugs in the cell array and peripheral circuit regions of the integrated circuit substrate  
Integrated circuit devices, for example, dynamic random access memory (DRAM) devices, are provided including an integrated circuit substrate having a cell array region and a peripheral circuit...
7489027 Accessible electronic storage apparatus  
A storage apparatus 10 is disclosed, that comprises a wiring substrate 11 having a first surface and a second surface, a flat type external connection terminal 12 a disposed on the first...
7488637 CMOS image sensor and method for forming the same  
A CMOS image sensor and a method for forming the same are provided. According to the method, a gate insulating layer and a doped polysilicon layer which are sequentially stacked on a substrate are...
7482668 Semiconductor device  
A semiconductor device is provided. A transistor is formed on a substrate, and a metal silicide layer is formed on the surface of a gate conductor layer and a source/drain region. Next, a surface...
7476943 Semiconductor device having diffusion layers as bit lines and method for manufacturing the same  
A semiconductor device includes: a semiconductor region; a plurality of bit line diffusion layers formed in an upper portion of the semiconductor region and each extending in a row direction; a...
7473627 Semiconducting device having a structure to improve contact processing margin, and method of fabricating the same  
A method for fabricating a semiconductor device includes forming a first insulating pattern, a first conductive pattern, and a second conductive pattern on a semiconductor substrate; forming a...
7465996 Semiconductor device and method for fabricating the same  
A semiconductor device includes: a semiconductor substrate divided into a first region and a second region; a first MIS transistor formed in the first region of the semiconductor substrate and...
7456472 Semiconductor device and manufacturing method thereof  
A semiconductor device comprising a multi Fin-FET structure capable of suppressing short channel effects, controlling a threshold voltage, driving a high current, and operating in a high-speed...
7453120 Semiconductor structure  
A method for fabricating a semiconductor structure is described. A substrate is provided, having thereon a gate structure and a spacer on the sidewall of the gate structure and having therein an...
7448395 Process method to facilitate silicidation  
The present invention substantially removes dry etch residue from a dry plasma etch process 110 prior to depositing a cobalt layer 124 on silicon substrate and/or polysilicon material....
7446379 Transistor with dopant-bearing metal in source and drain  
A transistor and method of manufacturing thereof. A gate dielectric and gate are formed over a workpiece, and the source and drain regions of a transistor are recessed. The recesses are filled with...
7446044 Carbon nanotube switches for memory, RF communications and sensing applications, and methods of making the same  
Switches having an in situ grown carbon nanotube as an element thereof, and methods of fabricating such switches. A carbon nanotube is grown in situ in mechanical connection with a conductive...
7439571 Method for fabricating metal gate structures  
Methods of forming a microelectronic structure are described. Those methods comprise providing a substrate comprising source/drain and gate regions, wherein the gate region comprises a metal layer...
7439566 Semiconductor memory device having metal-insulator transition film resistor  
A semiconductor memory device may have a lower leakage current and/or higher reliability, e.g., a longer retention time and/or a shorter refresh time. The device may include a switching device and...
7436017 Semiconductor integrated circuit using a selective disposable spacer  
Methods of manufacturing a semiconductor integrated circuit using selective disposable spacer technology and semiconductor integrated circuits manufactured thereby: The method includes forming a...
7432560 Body-tied-to-source MOSFETs with asymmetrical source and drain regions and methods of fabricating the same  
A metal oxide semiconductor field effect transistor (MOSFET) includes a body pattern of a first conductivity type disposed on an insulating layer. A gate electrode is disposed on the body pattern....
7405449 Semiconductor device and method of manufacturing the same  
A semiconductor device includes a semiconductor substrate, and a MOS transistor provided on the semiconductor substrate and having a channel type of a first conductivity, the MOS transistor...
7402872 Method for forming an integrated circuit  
A method is described for manufacturing an n-MOS semiconductor transistor. Recesses are formed in a semiconductor substrate adjacent a gate electrode structure. Silicon is embedded in the recesses...
7397131 Self-aligned semiconductor contact structures  
A self-aligned contact structure and a method of forming the same include selected neighboring gate electrodes with adjacent sidewalls that are configured to angle toward each other. The angled...
7385294 Semiconductor device having nickel silicide and method of fabricating nickel silicide  
A semiconductor device having nickel silicide and a method for fabricating nickel silicide. A semiconductor substrate having a plurality of doped regions is provided. Subsequently, a nickel layer...
7385259 Method of manufacturing a multilayered doped conductor for a contact in an integrated circuit device  
A method of manufacturing a memory device addressing reliability and refresh characteristics through the use of a multilayered doped conductor, and a method making is described. The multilayered...
7385258 Transistors having v-shape source/drain metal contacts  
A semiconductor structure and a method for forming the same. The semiconductor structure includes (a) a semiconductor layer, (b) a gate dielectric region, and (c) a gate electrode region. The gate...
7355255 Nickel silicide including indium and a method of manufacture therefor  
The present invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among...
7355254 Pinning layer for low resistivity N-type source drain ohmic contacts  
A system or apparatus including an N-type transistor structure including a gate electrode formed on a substrate and source and drain regions formed in the substrate; a contact to the source region;...
7348613 CMOS imager with selectively silicided gates  
The invention also relates to an apparatus and method for selectively providing a silicide coating over the transistor gates of a CMOS imager to improve the speed of the transistor gates. The...
7342286 Electrical node of transistor and method of forming the same  
According to example embodiments of the present invention, there are provided an electrical node of a transistor and a method of forming the same, which may reduce or minimize current leakage...
7342273 Applying epitaxial silicon in disposable spacer flow  
A process for forming active transistors for a semiconductor memory device by the steps of: forming transistor gates having generally vertical sidewalls in a memory array section and in periphery...
Matches 1 - 50 out of 590 1 2 3 4 5 6 7 8 9 10 11 12 >