Matches 1 - 50 out of 263 1 2 3 4 5 6 >
Match Document Document Title
7629655 Semiconductor device with multiple silicide regions  
A system and method for forming a semiconductor device with a reduced source/drain extension parasitic resistance is provided. An embodiment comprises implanting two metals (such as ytterbium and...
7629646 Trench MOSFET with terraced gate and manufacturing method thereof  
A trench metal oxide semiconductor field effect transistor (MOSFET) with a terraced trench gate. An epitaxial layer with a plurality of trenches is provided and a gate oxide layer is covered the...
7615829 Elevated source and drain elements for strained-channel heterojuntion field-effect transistors  
A semiconductor structure having a surface layer disposed over a substrate, the surface layer including strained silicon. A contact layer is disposed over a portion of the surface layer, the...
7612416 Semiconductor device having a conductive portion below an interlayer insulating film and method for producing the same  
A semiconductor device comprising: a MIS type field effect transistor which comprises a semiconductor raised portion protruding from a substrate plane, a gate electrode extending over the...
7573106 Semiconductor device and manufacturing method therefor  
A method of manufacturing a semiconductor device comprises forming a gate insulation film on a semiconductor substrate; forming a first gate electrode and a second gate electrode on the gate...
7528450 Semiconductor device having NMOSFET and PMOSFET and manufacturing method therefor  
A element isolation insulating film is formed around the device regions in the silicon substrate. The device regions are formed an n-type diffusion layer region, a p-type diffusion layer region, a...
7498641 Partial replacement silicide gate  
A method of forming fully silicide gates having uniform gate silicide thickness is presented. A gate dielectric is formed over a substrate. A silicon-containing layer is formed over the gate...
7488637 CMOS image sensor and method for forming the same  
A CMOS image sensor and a method for forming the same are provided. According to the method, a gate insulating layer and a doped polysilicon layer which are sequentially stacked on a substrate are...
7482668 Semiconductor device  
A semiconductor device is provided. A transistor is formed on a substrate, and a metal silicide layer is formed on the surface of a gate conductor layer and a source/drain region. Next, a surface...
7479682 Structure of a field effect transistor having metallic silicide and manufacturing method thereof  
A field effect transistor having metallic silicide layers is formed in a semiconductor layer on an insulating layer of an SOI substrate. The metallic silicide layers are composed of refractory...
7473623 Providing stress uniformity in a semiconductor device  
A method includes forming a plurality of functional features on a semiconductor layer in a first region. A non-functional feature corresponding to the functional feature is formed adjacent at least...
7453133 Silicide/semiconductor structure and method of fabrication  
A preferred embodiment of the present invention comprises a dielectric/metal/2 nd energy bandgap (E g ) semiconductor/1 st E g substrate structure. In order to reduce the contact resistance, a...
7432559 Silicide formation on SiGe  
A semiconductor structure includes a first silicon-containing layer comprising an element selected from the group consisting essentially of carbon and germanium wherein the silicon-containing layer...
7427796 Semiconductor device and method of manufacturing a semiconductor device  
A semiconductor device according to an embodiment of the present invention comprises a first transistor including: a first source layer and a first drain layer both formed in one surface of a...
7419913 Methods of forming openings into dielectric material  
This invention includes methods of forming openings into dielectric material. In one implementation, an opening is partially etched through dielectric material, with such opening comprising a...
7405450 Semiconductor devices having high conductivity gate electrodes with conductive line patterns thereon  
Semiconductor devices that include a semiconductor substrate and a gate line are provided. The gate line is on the semiconductor substrate and includes a gate insulation pattern and a gate...
7355248 Metal oxide semiconductor (MOS) device, metal oxide semiconductor (MOS) memory device, and method of manufacturing the same  
A semiconductor device includes a first semiconductor layer that is formed on a first insulating layer; a second insulating layer that is formed on the first semiconductor layer; a second...
7329927 Integrated circuit devices having uniform silicide junctions  
Integrated circuit devices are provided including an integrated circuit substrate and a gate on the integrated circuit substrate. The gate has sidewalls. A barrier layer spacer is provided on the...
7327001 PMOS transistor with compressive dielectric capping layer  
A salicide layer is deposited on the source/drain regions of a PMOS transistor. A dielectric capping layer having residual compressive stress is formed on the salicide layer by depositing a...
7326648 Semiconductor device and fabrication process of forming silicide layer on a polysilicon pattern by reducing thickness of metal layer before forming silicide layer on the polysilicon pattern  
A semiconductor device includes a substrate having first and second device regions separated from each other by a device isolation region, a first field effect transistor having a first polysilicon...
7297618 Fully silicided gate electrodes and method of making the same  
The present invention relates to a method of selectively fabricating metal gate electrodes in one or more device regions by fully siliciding (FUSI) the gate electrode. The selective formation of...
7271412 Active matrix organic light emitting device having series thin film transistor, and fabrication method therefor  
The series TFT comprises a semiconductor layer including a first body, a second body and a connecting portion serially connecting the first body to the second body. The first body has a first...
7265400 Semiconductor device including field-effect transistor using salicide (self-aligned silicide) structure and method of fabricating the same  
An element isolation region for electrically isolating an element region where an element is to be formed is formed in a semiconductor substrate. A gate insulating film is formed on the...
7265424 Fin Field-effect transistor and method for producing a fin field effect-transistor  
A fin field effect transistor having a substrate, a fin structure above the substrate, as well as a drain region and a source region outside the fin structure above the substrate. The fin structure...
7247915 Cobalt/nickel bi-layer silicide process for very narrow line polysilicon gate technology  
A silicide method for integrated circuit and semiconductor device fabrication wherein a layer of nickel is formed over at least one silicon region of a substrate and a layer of cobalt is formed...
7244977 Longitudinal MISFET manufacturing method, longitudinal MISFET, semiconductor storage device manufacturing method, and semiconductor storage device  
A semiconductor memory device includes a vertical MISFET having a source region, a channel forming region, a drain region, and a gate electrode formed on a sidewall of the channel forming region...
7244988 Semiconductor apparatus and method of manufacturing the same  
A semiconductor apparatus is disclosed. The semiconductor apparatus comprises a gate electrode formed on a surface of a semiconductor substrate with a gate insulating film provided therebetween....
7230286 Vertical FET with nanowire channels and a silicided bottom contact  
A vertical FET structure with nanowire forming the FET channels is disclosed. The nanowires are formed over a conductive silicide layer. The nanowires are gated by a surrounding gate. Top and...
7208805 Structures comprising a layer free of nitrogen between silicon nitride and photoresist  
The invention includes a semiconductor processing method. A first material comprising silicon and nitrogen is formed. A second material is formed over the first material, and the second material...
7190035 Semiconductor device having elevated source/drain on source region and drain region  
A semiconductor device disclosed herein comprises: an element isolation insulator which is formed on the surface side of a semiconductor substrate to provide electrical insulation from other...
7190036 Transistor mobility improvement by adjusting stress in shallow trench isolation  
A method of improving transistor carrier mobility by adjusting stress through recessing shallow trench isolation is presented. A trench is formed in a substrate. The trench is filled with a...
7189644 CMOS device integration for low external resistance  
The present invention relates to a Complementary Metal Oxide Semiconductor (CMOS) device having a lower external resistance and a method for manufacturing the CMOS device. The inventive MOSFET is...
7176525 Process for production of SOI substrate and process for production of semiconductor device  
A process for producing an adhered SOI substrate without causing cracking and peeling of a single-crystal silicon thin film. The process consists of selectively forming a porous silicon layer in a...
7176533 Semiconductor devices having contact plugs including polysilicon doped with an impurity having a lesser diffusion coefficient than phosphorus  
Forming a semiconductor device can include forming an insulating layer on a semiconductor substrate including a conductive region thereof, wherein the insulating layer has a contact hole therein...
7176523 Power mosfet having conductor plug structured contacts  
In a high frequency amplifying MOSFET having a drain offset region, the size is reduced and the on-resistance is decreased by providing conductor plugs 13 (P 1 ) for leading out electrodes on a...
7145205 Semiconductor device  
A semiconductor device includes: a semiconductor substrate having two types of active regions that are a PMOS region and an NMOS region separated from each other in plan view by a PN separation...
7135774 Heat resistant ohmic electrode and method of manufacturing the same  
An aspect of the present invention provides an ohmic electrode that includes an SiC (silicon carbide) substrate, an impurity region selectively formed in a surface of the SiC substrate, an...
7129547 Method of fabricating a high performance MOSFET device featuring formation of an elevated source/drain region  
A method of fabricating a MOSFET device featuring a raised source/drain structure on a heavily doped source/drain region as well as on a portion of a lightly doped source/drain (LDD), region, after...
7115949 Method of forming a semiconductor device in a semiconductor layer and structure thereof  
In some embodiments, non-volatile memory (NVM) devices are formed on a silicon-on-insulator (SOI) substrate ( 12 ) by forming elevated sources and drains ( 56 ) in contact with extensions ( 46 )...
7109109 Contact plug in semiconductor device and method of forming the same  
Disclosed are a contact plug in a semiconductor device and method of forming the same. After a junction region where a contact plug is formed upwardly up to the bottom of a metal wire, the raised...
7102201 Strained semiconductor device structures  
Semiconductor fabrication methods and structures, devices and integrated circuits characterized by enhanced operating performance. The structures generally include first and second source/drain...
7102167 Method and system for providing a CMOS output stage utilizing a buried power buss  
A CMOS output stage is disclosed. The CMOS output stage comprises a substrate and at least one well coupled to the substrate. The CMOS output stage also includes a plurality of slots provided...
7098478 Semiconductor memory device using vertical-channel transistors  
The invention provides a semiconductor memory device comprising a plurality of word lines, a plurality of bit lines, and a plurality of static memory cells each having a first, second, third,...
7081655 Formation of abrupt junctions in devices by using silicide growth dopant snowplow effect  
A method of forming an abrupt junction device with a semiconductor substrate is provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed on the gate dielectric. A...
7075157 Method of manufacturing a semiconductor integrated circuit device  
Disclosed is a semiconductor integrated circuit device (e.g., an SRAM) having memory cells each of a flip-flop circuit constituted by and a pair of load MISFETs, the MISFETs being cross-connected...
7075158 Semiconductor device and method of manufacturing the same  
A semiconductor device can be manufactured which has a low resistance, and device characteristics of which do not vary. The semiconductor device includes a silicon layer, a gate dielectric film...
7045864 Semiconductor integrated circuit device  
A semiconductor integrated circuit device, e.g., a memory cell of an SRAM, is formed of a pair of inverters having their input and output points connected in a crisscross manner and being formed of...
7026211 Semiconductor component and method of manufacture  
A semiconductor component having smooth, void-free conductive layers and a method for manufacturing the semiconductor component. Surface features such as gate structures are formed on a...
7023047 MOS device and process for manufacturing MOS devices using dual-polysilicon layer technology  
An MOS device has a stack and a passivation layer covering the stack. The stack is formed by a first polysilicon region and by a second polysilicon region arranged on top of one another and...
6995432 Semiconductor device having a gate oxide film with some NTFTS with LDD regions and no PTFTS with LDD regions  
A MIS type semiconductor device and a method for fabricating the same characterized in that impurity regions are selectively formed on a semiconductor substrate or semiconductor thin film and are...
Matches 1 - 50 out of 263 1 2 3 4 5 6 >