Patents in Class 257/372

Matches 1 - 50 out of 319

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Match	Document	Document Title
1	7629654	Buried guard ring structures and fabrication methods Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation....
2	7615828	CMOS devices adapted to prevent latchup and methods of manufacturing the same In a first aspect, a first apparatus is provided. The first apparatus is a semiconductor device on a substrate that includes (1) a first metal-oxide-semiconductor field-effect transistor (MOSFET);...
3	7612422	Structure for dual work function metal gate electrodes by control of interface dipoles Exemplary embodiments provide structures for dual work function metal gate electrodes. The work function value of a metal gate electrode can be increased and/or decreased by disposing various...
4	7612414	Overlapped stressed liners for improved contacts A semiconductor structure is provided which includes a first semiconductor device in a first active semiconductor region and a second semiconductor device in a second active semiconductor region. A...
5	7595534	Layers in substrate wafers The invention relates to layers in substrate wafers. The aim of the invention is to provide layers in substrate wafers with which the drawbacks of conventional assemblies are overcome in order to...
6	7541652	Substrate coupled noise isolation for integrated circuits An integrated circuit includes a substrate, a noise sensitive circuit, and a first low impedance guard ring. The substrate includes a well-doped blocking ring that at least partially surrounds the...
7	7521762	Semiconductor integrated circuit device operating with low power consumption Transistors having large gate tunnel barriers are used as transistors to be on in a standby state, MIS transistors having thin gate insulating films are used as transistors to be off in the standby...
8	7518512	Transponder device A transponder device comprises an integrated CMOS circuit with a semiconductor substrate. A first rectifying diode (DS) is formed by the substrate diode of the CMOS circuit. A first MOS transistor...
9	7514754	Complementary metal-oxide-semiconductor transistor for avoiding a latch-up problem A semiconductor device is provided. The semiconductor device includes a substrate, a first epitaxial layer, a first sinker, a first buried layer, a second epitaxial layer, a second sinker and a...
10	7491618	Methods and semiconductor structures for latch-up suppression using a conductive region Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The semiconductor structure comprises first and second adjacent doped wells formed in the semiconductor material...
11	7442996	Structure and method for enhanced triple well latchup robustness Disclosed is a triple well CMOS device structure that addresses the issue of latchup by adding an n+ buried layer not only beneath the p-well to isolate the p-well from the p− substrate but also...
12	7429771	Semiconductor device having halo implanting regions A MIS-type semiconductor device includes a p-type semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, and...
13	7402859	Field effect semiconductor switch and method for fabricating it A field effect semiconductor comprises a semiconductor layer having a surface, a first and a second semiconductor region in the semiconductor layer, which are arranged next to one another at the...
14	7391200	P-channel power chip An integrated circuit device for delivering power to a load includes a P-MOS power transistor, an N-MOS bypass transistor and a gate driver circuit. The P-MOS power transistor is coupled between a...
15	7391069	Semiconductor device and manufacturing method thereof In a conventional semiconductor device, for example, a MOS transistor, there is a problem that a parasitic transistor is prone to be operated due to an impurity concentration in a back gate region...
16	7388260	Structure for spanning gap in body-bias voltage routing structure Structures for spanning gap in body-bias voltage routing structure. In an embodiment, a structure is comprised of at least one metal wire.
17	7358573	Triple-well CMOS devices with increased latch-up immunity and methods of fabricating same A triple-well CMOS structure having reduced latch-up susceptibility and a method of fabricating the structure. The method includes forming a buried P-type doped layer having low resistance under...
18	7355250	Electrostatic discharge device with controllable holding current An electrostatic discharge (ESD) device with a parasitic silicon controlled rectifier (SCR) structure and controllable holding current is provided. A first distance is kept between a first N+ doped...
19	7348637	Semiconductor device and method of manufacturing the same A semiconductor device including plural CMOS transistors with first and second transistors sharing a common first gate electrode and third and fourth transistors sharing a common second gate...
20	7326977	Low noise field effect transistor An FET (field effect transistor) having source, drain and channel regions of a conductivity type in a semiconductor body of opposite conductivity type. The channel region is located at the lower...
21	7323753	MOS transistor circuit and voltage-boosting booster circuit To an output of an NMOS having one end connected to a power source, a capacitor and a PMOS are connected. A capacitor is connected to the output of the PMOS. The NMOS and the PMOS are turned on...
22	7309898	Method and apparatus for providing noise suppression in an integrated circuit A method and apparatus for improving the latchup tolerance of circuits embedded in an integrated circuit while avoiding the introduction of noise from such tolerance into the power rails.
23	7304354	Buried guard ring and radiation hardened isolation structures and fabrication methods Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation....
24	7282771	Structure and method for latchup suppression A method and structure for an integrated circuit comprising a substrate of a first polarity, a merged triple well region of a second polarity and a doped region of the second polarity abutting the...
25	7271453	Buried biasing wells in FETS A structure of a semiconductor device and method for fabricating the same is disclosed. The semiconductor structure comprises first and second source/drain regions; a channel region disposed...
26	7271452	Analog switch An analog switch has a first circuit and a second circuit. The first circuit has an NMOS and PMOS connected in series, and the second circuit has a PMOS and NMOS connected in series. The first and...
27	7205614	High density ROM cell A high density read-only memory (ROM) cell is installed on a silicon substrate for storing data. The ROM cell includes a first doped region being of a second conductive type installed on the...
28	7196393	Semiconductor device including a high voltage transistor A drain diffusion layer 11 b includes a low impurity concentration region 5 a and a high impurity concentration region 5 b , and the low impurity concentration region 5 a is located on the...
29	7180142	Semiconductor device The present invention provides a semiconductor device having an active region bent at right angles, wherein an interval between patterns for the active region and a gate is set larger than an arc...
30	7176527	Semiconductor device and method of fabricating same A semiconductor device and a method of fabricating the same suppress a substrate floating effect without causing lowering of a degree of integration. The semiconductor device has a...
31	7145191	P-channel field-effect transistor with reduced junction capacitance The source/drain zones ( 140 and 142 or 160 and 162 ) of a p-channel IGFET ( 120 or 122 ) are provided with graded-junction characteristics to reduce junction capacitance, thereby...
32	7112856	Semiconductor device having a merged region and method of fabrication A semiconductor device includes an insulated gate electrode pattern formed on a well region. The semiconductor device further includes a sidewall spacer formed on sidewalls of the gate electrode...
33	7098512	Layout patterns for deep well region to facilitate routing body-bias voltage Layout patterns for the deep well region to facilitate routing the body-bias voltage in a semiconductor device are provided and described. The layout patterns include a diagonal sub-surface mesh...
34	7091564	Semiconductor chip with fuse unit A semiconductor chip includes a logic circuit unit, at least one memory macro unit having a redundant memory cell which recovers a defect cell, electrode pad rows being arranged around the outside...
35	7067883	Lateral high-voltage junction device A lateral high-voltage junction device for over-voltage protection of an MOS circuit includes a substrate having a first junction region separated from a second junction region by a substrate...
36	7057238	Semiconductor device and method for fabricating the same A semiconductor device and a method for fabricating the same are provided. The provided semiconductor device includes a field oxide layer formed in a semiconductor substrate to define an active...
37	7012309	High-voltage integrated CMOS circuit The invention relates to an integrated CMOS circuit comprising, in a semiconductor substrate ( 1 ) with a first type of conductivity, a casing ( 2 ) of a second type of retrograde-doped...
38	7009257	Methods of manufacturing integrated circuit devices having reduced contact resistance between a substrate and a contact pad while maintaining separation of the substrate and the contact pad and integrated circuit devices formed thereby An integrated circuit device includes a substrate that has a source region and a drain region formed therein. A gate pattern is disposed on the substrate between the source region and the drain...
39	7009255	Semiconductor device having punch-through structure off-setting the edge of the gate electrodes A semiconductor device and a method of manufacturing the same is disclosed. A trench is formed in an active region of a semiconductor substrate. A doped layer is formed on the inner walls of the...
40	6995435	Apparatus and circuit having reduced leakage current and method therefor Briefly, in accordance with one embodiment of the invention, an integrated circuit has a voltage generator that selectively increases the voltage potential on the channel region of a transistor...
41	6995432	Semiconductor device having a gate oxide film with some NTFTS with LDD regions and no PTFTS with LDD regions A MIS type semiconductor device and a method for fabricating the same characterized in that impurity regions are selectively formed on a semiconductor substrate or semiconductor thin film and are...
42	6979908	Input/output architecture for integrated circuits with efficient positioning of integrated circuit elements A described embodiment of the present invention includes an integrated circuit having a plurality of I/O modules. The I/O modules include a bond pad formed on a substrate. The I/O modules also...
43	6967381	Semiconductor device In order to improve the robustness against electrostatic discharge, when power source terminal and ground terminal are open, of a semiconductor device having a first, a second and a third inverter...
44	6967380	CMOS device having retrograde n-well and p-well A method of forming retrograde n-wells and p-wells. A first mask is formed on the substrate and the n-well implants are carried out. Then the mask is thinned, and a deep p implant is carried out...
45	6963113	Method of body contact for SOI MOSFET A new method for forming a silicon-on-insulator MOSFET while eliminating floating body effects is described. A silicon-on-insulator substrate is provided comprising a silicon semiconductor...
46	6956266	Structure and method for latchup suppression utilizing trench and masked sub-collector implantation A method and structure for an integrated circuit comprising a substrate of a first polarity; a trench structure in the substrate; a well region of a second polarity abutting the trench structure;...
47	6946710	Method and structure to reduce CMOS inter-well leakage A method of forming a semiconductor device with improved leakage control, includes: providing a semiconductor substrate; forming a trench in the substrate; forming a leakage stop implant in the...
48	6909150	Mixed signal integrated circuit with improved isolation An integrated circuit having improved isolation includes a first circuit section formed in a substrate and a second circuit section formed in the substrate, the second circuit section being spaced...
49	6878595	Technique for suppression of latchup in integrated circuits (ICS) The present invention relates to a technique that can be used to reduce the sensitivity of integrated circuits to a failure mechanism to which some integrated circuits (ICs) are susceptible, known...
50	6864547	Semiconductor device having a ghost source/drain region and a method of manufacture therefor The present invention provides a semiconductor device and a method of manufacture therefor. The semiconductor device includes a channel region located in a semiconductor substrate and a trench...

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